Internal Memory Access Listings - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Internal Memory Access Listings

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The operation of the shadow Write FIFO is fully transparent to the
user. The logic takes automatic control about SIMD, LW or
unaligned access types. Moreover it is able to handle sequential 32
to 40-bit data type access since the address may be the same.
Internal Memory Access Listings
The processor's DM and PM buses support many combinations of regis-
ter-to-memory data access options. The following factors influence the
data access type:
• Size of words—short word, normal word, extended-precision nor-
mal word, or long word
• Number of words—single or dual-data move
• Processor mode—SISD, SIMD, or broadcast load
The following list shows the processor's possible memory transfer modes
and provides a cross-reference to examples of each memory access option
that stems from the processor's data access options.
These modes include the transfer options that stem from the following
data access options:
• The mode of the processor: SISD, SIMD, or Broadcast Load
• The size of access words: long, extended-precision normal word,
normal word, or short word
• The number of transferred words
To take advantage of the processor's data accesses to three and four col-
umn locations, programs must adjust the interleaving of data into memory
locations to accommodate the memory access mode. The following
guidelines provide overviews of how programs should interleave data in
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