Chapter 1. Cyclone Iv Transceivers Architecture Transceiver Architecture - Altera Cyclone IV Device Handbook

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Architecture
Figure 1–2. F484 and Larger Packages with Transceiver Channels for Cyclone IV GX Devices
For more information about the transceiver architecture, refer to the following
sections:
■ "Architectural Overview" on page 1–4
■ "Transmitter Channel Datapath" on page 1–5
"Receiver Channel Datapath" on page 1–11
■
■ "Transceiver Clocking Architecture" on page 1–26
■ "Transceiver Channel Datapath Clocking" on page 1–29
■ "FPGA Fabric-Transceiver Interface Clocking" on page 1–43
"Calibration Block" on page 1–45
■
"PCI-Express Hard IP Block" on page 1–46
■
February 2015 Altera Corporation
MPLL_8 GPLL_2
Channel 3
Channel 2
Transceiver
Block GXBL1
Channel 1
Channel 0
MPLL_7
MPLL_6
Channel 3
Channel 2
Transceiver
Block GXBL0 Channel 1
Channel 0
Calibration Block
MPLL_5 GPLL_1
F484 and larger
packages
Not applicable in
F484 package
PCIe
hard IP
Cyclone IV Device Handbook,
1–3
Volume 2