Control Registers - Altera Nios II User Manual

Chapter 3: Programming Model
Registers
f
For more information, refer to the
Processor Reference Handbook.

Control Registers

Control registers report the status and change the behavior of the processor. Control
registers are accessed differently than the general-purpose registers. The special
instructions rdctl and wrctl provide the only means to read and write to the control
registers and are only available in supervisor mode.
1
When writing to control registers, all undefined bits must be written as zero.
The Nios II architecture supports up to 32 control registers. All nonreserved control
registers have names recognized by the assembler.
Table 3–6. Control Register Names and Bits
Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16–31
Notes:
(1) Available only when the external interrupt controller interface is not present. Otherwise reserved.
(2) Available only when the MMU is present. Otherwise reserved.
(3) Available only when ECC is present.
(4) Available only when the MPU is present. Otherwise reserved.
The following sections describe the nonreserved control registers.
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Application Binary Interface
Name
Refer to
status
Refer to
estatus
Refer to
bstatus
Internal interrupt-enable bits
ienable
Pending internal interrupt bits
ipending
Unique processor identifier
cpuid
Reserved Reserved
Refer to
exception
(2) Refer to
pteaddr
(2) Refer to
tlbacc
(2) Refer to
tlbmisc
(3) Refer to
eccinj
Refer to
badaddr
(4) Refer to
config
(4) Refer to
mpubase
(4) Refer to
mpuacc
Reserved Reserved
Register Contents
Table 3–7 on page 3–12
Table 3–9 on page 3–13
Table 3–10 on page 3–14
(1)
(1)
Table 3–12 on page 3–15
Table 3–13 on page 3–15
Table 3–15 on page 3–16
Table 3–17 on page 3–17
Table 3–31 on page 3–25
Table 3–19 on page 3–20
Table 3–21 on page 3–20
Table 3–23 on page 3–21
Table 3–25 on page 3–22
Nios II Processor Reference Handbook
3–11
chapter of the Nios II