Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 1021

In bypass mode, if the least significant bit (LSB) of the
set to 1, then a one-shot pulse is generated. This one-shot-pulse has a
duration equal to the period of
for unit C, and
MISCA4_I
ities" on page 9-24). This pulse is generated either at the rising or at the
falling edge of the input clock, depending on the value of the
, , and
INVFSB INVFSC
31 30
INVFSB
Active Low Frame Sync B/D
15
INVFSA
Active Low Frame Sync A/C
Figure A-104. PCG_PWx Registers (in Bypass Mode)
Table A-101. PCG_PWx Register Bit Descriptions
(in Bypass Mode) (RW)
Bit Name
0 STROBEx
1 INVFSx
15–2 Reserved (In bypass mode, bits 15-2 are ignored.)
16 STROBEx
ADSP-214xx SHARC Processor Hardware Reference
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MISCA2_I
MISCA5_I
bits of the
INVFSD
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
Description
One Shot Frame Sync A/C. Frame sync is a pulse with dura-
tion equal to one period of the MISCA2_I signal (PCG A)
MISCA4_I signal (PCG C) repeating at the beginning of
every frame.
Note: This is valid in bypass mode only.
Active Low Frame Sync Select for Frame Sync A/C.
0 = Active high frame sync
1 = Active low frame sync
One Shot Frame Sync B/D. Frame sync is a pulse with dura-
tion equal to one period of the MISCA3_I signal (PCG B)
MISCA5_I signal (PCG D) repeating at the beginning of
every frame.
Note: This is valid in bypass mode only.
Registers Reference
for unit A,
MISCA3_I
for unit D (see "DAI Routing Capabil-
and
PCG_PW PCG_PW2
21 20 19 18 17 16
6 5 4 3 2 1 0
register is
PCG_PW
for unit B,
,
INVFSA
registers.
STROBEB
One Shot Frame Sync B/D
STROBEA
One Shot Frame Sync A/C
A-195