Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 1005

15 14 13 12 11 10 9 8
Figure A-95. IDP_CTL2 Register
Table A-92. IDP_CTL2 Register Bit Descriptions (RW)
Bit Name
7–0 FAEx
8–31 Reserved
Parallel Data Acquisition Port Control Register
(IDP_PP_CTL)
The
IDP_PP_CTL
Table A-93) provides 20 mask bits that allow the input from any of the 20
pins to be ignored.
For more information on the operation of the parallel data acquisition
port, see Chapter 11, Input Data
ing that is used in conjunction with this module, see
on page 23-28.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
7 6 5 4 3 2 1 0
Description
First Active Edge for Channel x.
1= nth IDP channel starts shifting in data from the first ris-
ing edge of LRCLK after IDP is enabled. This data is
latched after the next falling edge of LRCLK.
0 = nth IDP channel starts shifting in data from the first
falling edge of LRCLK after IDP is enabled. This data is
latched after the next rising edge of LRCLK. Reset value of
all these bits is 0. These bits are used only if IDP_INTEN
bit (IDP_CTL1[24]) is set.
register (shown in Figure A-96
Port. For information on the pin mux-
Registers Reference
FAEx (7–0)
First Active Edge for
Channel x
and described in
"Pin Multiplexing"
A-179