Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 1030

Peripherals Routed Through the DAI
Table A-108. DITUSRBITBx Registers (RW)
Register
DITUSRBITB0
DITUSRBITB1
DITUSRBITB2
DITUSRBITB3
DITUSRBITB4
DITUSRBITB5
User Bit Update Register (DITUSRUPD)
This register is a 1-bit wide register (WO). After writing to the user bits
registers (
DITURSBITAx
into
DITUSRUPD
transfer.
Receiver Registers
The following sections describe the receiver registers.
Receive Control Register (DIRCTL)
This 32-bit register, described in
trol and single-channel double-frequency mode.
A-204
www.BDTIC.com/ADI
Bits 7–0
BYTE0
BYTE4
BYTE8
BYTE12
BYTE16
BYTE20
and
DITUSRBITBx
register to enable the use of these bits in the next block of
Table A-109
ADSP-214xx SHARC Processor Hardware Reference
Bits 15–8 Bits 23–16
BYTE1 BYTE2
BYTE5 BYTE6
BYTE9 BYTE10
BYTE13 BYTE14
BYTE17 BYTE18
BYTE21 BYTE22
), a value of 0x1 must be written
is used to set up error con-
Bits 31–24
BYTE3
BYTE7
BYTE11
BYTE15
BYTE19
BYTE23