Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 1023

Table A-102. PCG_SYNC1 Register Bit Descriptions (RW)
Bit Name
0 FSA_SYNC
1 CLKA_SYNC
2 CLKA_SOURCE_IOP Enable Clock A Input Source.
3 FSA_SOURCE_IOP
16 FSB_SYNC
17 CLKB_SYNC
18 CLKB_SOURCE_IOP
19 FSB_SOURCE_IOP
ADSP-214xx SHARC Processor Hardware Reference
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Description
Enable Synchronization of Frame Sync A With External
Frame Sync.
0 = Frame sync disabled
1 = Frame sync enabled
Enable Synchronization of Clock A With External Frame
Sync.
0 = Clock disabled
1 = Clock enabled
0 = Output selected by CLKASOURCE bit
1 = PCLK selected for clock A.
Enable Frame Sync A Input Source.
0 = Output selected by FSASOURCE bit
1 = PCLK selected for frame sync A.
Enable Synchronization of Frame Sync B With External
Frame Sync.
0 = Frame sync disabled
1 = Frame sync enabled
Enable Synchronization of Clock B With External Frame
Sync.
0 = Clock disabled
1 = Clock enabled
EnabLe Clock B Input Source.
0 = Output selected by CLKBSOURCE bit
1 = PCLK selected for clock B.
Enable Frame Sync B Input Source.
0 = Output selected by FSBSOURCE bit
1 = PCLK selected for frame sync B.
Registers Reference
A-197