Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 1029

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Table A-106. DITCHANBx Registers (RW) (Cont'd)
Register
DITCHANB2
DITCHANB3
DITCHANB4
DITCHANB5
Transmit User Bits Buffer Registers for Subframe A/B
Registers (DITUSRBITAx/Bx)
Once programmed, these registers are used only for the next block of data.
This allows programs to change the user bit information with every block
of data. After writing to the appropriate registers to change the user bits
for the next block,
enable the use of these bits. Note these registers are used in standalone
mode only.
There are six user bits buffer registers associated with subframe A (left
channel) and six user bits buffer registers associated with subframe B
(right channel). These registers are listed with their locations in
Table A-107
and
Table A-107. DITUSRBITAx Registers (RW)
Register
DITUSRBITA0
DITUSRBITA1
DITUSRBITA2
DITUSRBITA3
DITUSRBITA4
DITUSRBITA5
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Bits 7–0
BYTE9
BYTE13
BYTE17
BYTE21
and
DITUSRBITAx
Table
A-108.
Bits 7–0
BYTE0
BYTE4
BYTE8
BYTE12
BYTE16
BYTE20
Registers Reference
Bits 15–8
Bits 23–16
BYTE10
BYTE11
BYTE14
BYTE15
BYTE18
BYTE19
BYTE22
BYTE23
must be written to
DITUSRBITBx
Bits 15–8
Bits 23–16
BYTE1
BYTE2
BYTE5
BYTE6
BYTE9
BYTE10
BYTE13
BYTE14
BYTE17
BYTE18
BYTE21
BYTE22
Bits 31–24
BYTE12
BYTE16
BYTE20
Reserved
Bits 31–24
BYTE3
BYTE7
BYTE11
BYTE15
BYTE19
BYTE23
A-203

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