Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 1000

Peripherals Routed Through the DAI
SPORT Error Status Register (SPERRSTAT)
The
SPERRSTAT
Figure A-92).
31 30
SP7 FSERR
SP6 FSERR
SP5 FSERR
SP4 FSERR
15 14 13
SP7 DERRB
SP7 DERRA
SP6 DERRB
SP6 DERRA
SP5 DERRB
SP5 DERRA
SP4 DERRB
SP4 DERRA
Figure A-92. SPERRSTATx Register (RO)
Input Data Port Registers
The input data port (IDP) provides an additional input path to the pro-
cessor core. The IDP can be configured as 8 channels of serial data or 7
channels of serial data and a single channel of up to a 20-bit wide parallel
data.
Input Data Port DMA Control Registers
For information on these registers, see
ters" on page 2-4.
A-174
www.BDTIC.com/ADI
register checks the status of SPORT interrupts (see
29 28 27 26 25 24 23 22
12 11 10 9 8 7 6
ADSP-214xx SHARC Processor Hardware Reference
21 20 19 18 17 16
SP0 FSERR
SP1 FSERR
SP2 FSERR
SP3 FSERR
5 4 3 2 1 0
SP0 DERRA
SP0 DERRB
SP1 DERRA
SP1 DERRB
SP2 DERRA
SP2 DERRB
SP3 DERRA
SP3 DERRB
"Standard DMA Parameter Regis-