Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 1063

DMA Configuration Registers (SPIDMAC,
SPIDMACB)
These 17-bit SPI registers are used to control DMA transfers and are
shown in Figure A-133
31 30
SPICHS
DMA Chain Loading Status
15
SPIDMAS
DMA Transfer Status
SPIERRS
DMA Error Status
SPISx (13–12)
DMA FIFO Status
SPIMME
Multimaster Error
SPIUNF
Transmit Underflow Error
SPIOVF
Receive Overflow Error
INTERR
Enable Interrupt on Error
Figure A-133. SPIDMAC, SPIDMACB Registers
Table A-123. SPIDMAC, SPIDMACB Register Bit Descriptions
(RW)
Bit Name
0 SPIDEN
1 SPIRCV
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
and described in
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
Description
DMA Enable.
0 = Disable
1 = Enable
DMA Write/Read.
0 = SPI transmit (read from internal memory)
1 = SPI receive (write to internal memory)
Registers Reference
Table A-123.
21 20 19 18 17 16
6 5 4 3 2 1 0
SPIDEN
DMA Enable
SPIRCV
DMA Write/Read
INTEN
Enable DMA Interrupt on Transfer
INTETC
Interrupt on External Transfer
Complete Enable
SPICHEN
SPI DMA Chaining Enable
FIFOFLSH
DMA FIFO Clear
A-237