Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 1025

Table A-103. PCG_SYNC2 Register Bit Descriptions (RW) (Cont'd)
Bit Name
17 CLKD_SYNC
18 CLKD_SOURCE_IOP
19 FSD_SOURCE_IOP
Sony/Philips Digital Interface Registers
The following sections describe the registers that are used to configure,
enable, and report status information for the S/PDIF transceiver.
Transmitter Registers
The following sections describe the S/PDIF transmitter registers.
Transmit Control Register (DITCTL)
This 32-bit register's bits are shown in
Table A-104.
ADSP-214xx SHARC Processor Hardware Reference
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Description
Enable Synchronization of Clock D With External Frame
Sync.
0 = Clock disabled
1 = Clock enabled
Enable Clock D Input Source.
0 = Output selected by CLKDSOURCE bit
1 = PCLK selected for clock D
Enable Frame Sync D Input Source.
0 = Output selected by FSDSOURCE bit
1 = PCLK selected for frame sync D
Figure A-107
Registers Reference
and described in
A-199