Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 995

SPORT Multichannel Control Registers (SPMCTLx)
The serial ports in the ADSP-214xx processors work individually, not in
pairs. Therefore, each SPORT has its own multichannel control register.
These registers are shown in
Note that in ADSP-2136x SHARC processors there is one
ter for each TDM pair, so its enough to write into one register, for both
SPORTs.
On the ADSP-214xx SHARC processors, each sport has its own
register, so only one write into both
SPMCTLx
to operate the SPORTs as pairs. Since there is no change in
ter bit definitions, the same value can be written into both
registers in order to make legacy programs for the ADSP-2136x processors
operate correctly.
DMACHSxB
SPORTx Channel B Status
DMA Chaining Status
DMACHSxA
SPORTx Channel A Status
DMA Chaining Status
DMACHSyB
SPORTx Channel B Status
DMA Chaining Status
DMACHSyA
SPORTx Channel A Status
DMA Chaining Status
DMASyB
SPORTx Channel B
DMA Status
15
SPL
SPORT Loopback
NCH (11–5)
Number of Channels – 1
Figure A-90. SPMCTLx Registers – Multichannel Mode
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Figure A-90
31 30 29 28 27 26 25 24
14 13 12 11 10 9 8
Registers Reference
and described in
registers is required
SPMCTLx
23 22 21 20 19 18 17 16
7 6 5 4 3 2 1 0
Table A-88.
regis-
SPMCTLxy
regis-
SPMCTLx
SPMCTLx
CHNL (22–16)
Current Channel Status
MCEB
Multichannel Enable
B Channels
DMASxA
SPORTx Channel A DMA
Status
DMASxB
SPORTx Channel B DMA
Status
DMASyA
SPORTx Channel A DMA
Status
MCEA
Multichannel Enable
A Channels
MFDx (4–1)
Multichannel Frame Delay
A-169