Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 998

Peripherals Routed Through the DAI
port is configured as transmitter. If the serial port is configured as the
receiver it ignores the incoming data.
SPORT Compand Registers (MTxCCSy or MRxCCSy)
Each bit, 31–0, set (=1) in one of the four
for SPORT/0/2/4/6 and
MTxCCS3
SPORT1/3/5/7 registers corresponds to a companded channel, 127–0, on
a multichannel mode serial port. When these registers activate compand-
ing for a channel, the SPORT applies the companding from the serial
port's selection to the word transmitted or received in that channel's
DTYPE
position of the data stream. When a channel's bit in these registers is
cleared (=0), the SPORT does not compand the outgoing or incoming
data during the channel's time slot.
Error Control Register (SPERRCTLx)
The
SPERRCTLx
generated by each SPORT (see
15 14 13
FSERR_STAT
Frame Sync Interrupt Status
DERRB_STAT
Channel B Interrupt Status
DERRA_STAT
Channel A Interrupt Status
Figure A-91. SPERRCTLx Register
A-172
www.BDTIC.com/ADI
MRxCCS0
registers control and report the status of the interrupts
Figure
12 11 10 9 8 7 6 5
ADSP-214xx SHARC Processor Hardware Reference
,
MTxCCS0 MTxCCS1
, ,
MRxCCS1 MRxCCS2
A-91, Table A-89).
4 3 2 1 0
DERRA_EN
Enable Channel A Error Detection
DERRB_EN
Enable Channel B Error Detection
FSERR_EN
Enable Frame Sync Error Detection
, ,
MTxCCS2
, for
MRxCCS3