Edge-Aligned Mode - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

PWM Implementation
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PWMGSTAT
PWMGCTL
PWM
CONFIGURATION
REGISTERS
PWMTM
PWMCTRL
PHB BUS
Timing
CLK SYNC SR RESET
PWM
Sync Pulse
Control Unit
Figure 8-1. Example PWM Module Block Diagram

Edge-Aligned Mode

In edge-aligned mode, the PWM waveform is left-justified in the period
window. A duty value of zero, programmed through the
produces a PWM waveform with 50% duty cycle. For even values of
period, the PWM pulse width is exactly period ÷ 2, whereas for odd values
8-2
GLOBAL
REGISTERS
PWM
DUTY CYCLE
REGISTERS
PWMCHA
PWMCHB
Dead
PWM
Time
Control
Unit
ADSP-21368 SHARC Processor Hardware Reference
PWMDT
PWMSEG
PWMSEG
Output
Control
Unit
Unit
SYNC
PWM
Interrupt
Control Unit
PWMSTAT
PWM_AH
Gate
PWM_AL
Drive
PWM_BH
Unit
PWM_BL
CLK
CLK
PWM_SYNC_IRQ
RESETB
registers,
PWMAx