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Push Buttons and Switches
Boot Mode Select Switch (SW4)
The boot mode select switch (
cessor.
Table 2-7
processor boots from the on-board parallel flash memory.
The selected position of
ing portion of the switch, not the small arrow.
Table 2-7. Boot Mode Select Switch (SW4)
SW4 Position
0
1
2
3
4
5
6
7
DSP Clock Configuration Switch (SW5)
The clock configuration switch (
processor at power up. The core to clock-in ratio is multiplied by the
25 MHz oscillator (
shows the switch settings.
The core clock frequency can be increased or decreased via software by
writing to the
2-10
SW4
shows the available boot mode settings. By default, the
is marked by the notch down the entire rotat-
SW4
Processor Boot Mode
SPI slave boot
Boot from SPI flash memory (SPI master boot)
Boot from 8-bit external parallel flash memory (default)
Reserved
Reserved
Reserved
Reserved
Reserved
) to produce the power up core frequency.
U7
register. For more information on changing the core
PMCTL
ADSP-21489 EZ-Board Evaluation System Manual
) determines the boot mode of the pro-
) controls the core frequency of the
SW5
Table 2-8
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