Receiving Link Port To Link Port - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Link Ports DMA
Table 7-13. Link to Internal/External Memory TCB
Receiver TCB Configuration
Register Field
DI
DX
DY
DP TY
DP PR
DP 2DDMA
DP LEN
DP INT
DP DRQ
DP CHEN
DP CHTG
DP CHPT
internal bus access to link port. Once the bus is granted, it drives
the data on the data bus. The transmitter
described in Table 7-14.

Receiving Link Port to Link Port

In order to move data from one link port to another link port, the receiver
should be programmed as a link
TCB
7-64
Description
Internal/external memory address
Number of words to transfer and address modifier. The
to X dimension data when the
Number of Y dimension words to transfer and address modifier when the
bit is set in the
2DDMA DP
Internal/external memory
Channel priority
1.......Increases the channel priority – internal/cluster bus DMA request
priority is high.
Sets the two-dimensional DMA mode
1 – Enables two-dimensional DMA mode; the
(See "Two-Dimensional DMA" on page 7-45.)
Always set to quad-word.
Sets interrupt
1 – Interrupts the core once the complete block is transferred.
Don't care (set in hardware).
Sets chaining
1 – Enables chaining.
Defines the register to be loaded; may be any link channel.
TCB
Chaining pointer – relevant if chaining is enabled.
TCB
ADSP-TS101 TigerSHARC Processor
bit is set in the
2DDMA
register; otherwise irrelevant.
DY
configuration is
TCB
. See Table 7-15.
Hardware Reference
register also refers
DX
register.
DP
register becomes relevant.