Digital Specifications; Dacclk_N), Added Dac Clock Rate - Analog Devices AD9739 Manual

4-bit, 2500 msps, rf digital-to-analog converter
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AD9739

DIGITAL SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I
link, unless otherwise noted.
Table 2.
Parameter
LVDS DATA INPUTS
(DB0[13:0]P, DB0[13:0]N, DB1[13:0]P, DB1[13:0]N) DB+ = V
Input Voltage Range, V
or V
IA
Input Differential Threshold, V
Input Differential Hysteresis, V
Receiver Differential Input Impedance, R
LVDS Input Rate
LVDS Minimum Data Valid Period (t
Input Capacitance
LVDS CLOCK INPUT
(DCI_P, DCI_N) DCI_P = V
IA
Input Voltage Range, V
or V
IA
Input Differential Threshold, V
Input Differential Hysteresis, V
Receiver Differential Input Impedance, R
Maximum Clock Rate
LVDS CLOCK OUTPUT
(DCO_P, DCO_N) DCO_P = V
Output Voltage High, V
or V
OA
Output Voltage Low, V
or V
OA
Output Differential Voltage, |V
Output Offset Voltage, V
OS
Output Impedance, Single-Ended, R
R
Mismatch Between A and B, ∆RO
O
Change in |V
| Between 0 and 1, |ΔV
OD
Change in V
Between 0 and 1, ∆V
OS
Output Current, Driver Shorted to Ground, I
Output Current, Drivers Shorted Together, I
Power-Off Output Leakage, |I
Maximum Clock Rate
DAC CLOCK INPUT (DACCLK_P, DACCLK_N)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
DAC Clock Rate
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (f
SCLK
Minimum Pulse Width High, t
Minimum Pulse Width Low, t
Minimum SDIO and CS to SCLK Setup, t
Minimum SCLK to SDIO Hold, t
Maximum SCLK to Valid SDIO and SDO, t
Minimum SCLK to Invalid SDIO and SDO, t
= 20 mA. LVDS drivers and receivers are compliant to the IEEE-1596 reduced range
FS
IB
IDTH
– V
IDTHH
IDTHL
IN
)
MDE
, DCI_N = V
IB
IB
IDTH
− V
IDTHH
IDTHL
IN
, DCO_N = V
100 Ω Termination
OA
OB
OB
OB
|
OD
O
|
OD
OS
, I
SA
SB
SAB
|, |I
|
XA
XB
, 1/t
)
SCLK
PWH
PWL
DS
DH
DV
DNV
Min
, DB−= V
IA
IB
825
−100
80
1250
825
−100
80
625
1025
150
1150
40
625
800
20
20
Rev. A | Page 4 of 56
Typ
Max
1575
+100
20
120
344
1.2
1575
+100
20
120
1375
200
250
1250
100
140
10
25
25
20
4
10
1.8
900
2500
20
10
5
20
5
Unit
mV
mV
mV
Ω
MSPS
ps
pF
mV
mV
mV
Ω
MHz
mV
mV
mV
mV
Ω
%
mV
mV
mA
mA
mA
MHz
V
mV
MSPS
MHz
ns
ns
ns
ns
ns
ns

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