Drive Strength Selection (Clock); Drive Strength Selection (Synchronization) - Analog Devices Advantiv ADV7604 Hardware Manual

3.5.6

Drive Strength Selection (Clock)

DR_STR_CLK[1:0], IO Map, Address 0x14, [3:2]
The DR_STR_CLK[1:0] bits allow the user to select the strength of the clock signal output driver
(LLC pin).
Refer to DR_STR[1:0]
synchronization, and audio output signals.
Function
DR_STR_CLK[1:0]
00
01
10
11
3.5.7

Drive Strength Selection (Synchronization)

DR_STR_SYNC[1:0], IO Map, Address 0x14, [1:0]
The DR_STR_SYNC[1:0] bits allow the user to select the strength of the following synchronization
signals:
• DE
• HS
• VS
• FIELD
• SYNC_OUT
Refer to DR_STR[1:0]
pixel clock, and audio output signals.
Function
DR_STR_SYNC[1:
0]
00
01
10
11
Rev. F August 2010
and DR_STR_SYNC[1:0]
Description
Reserved
Medium low drive strength (2X) for LLC1 up to 60 MHz
Medium high drive strength (3X) for LLC1 from 55 MHz to 105 MHz
High drive strength (4X) for LLC1 >100 MHz
and DR_STR_CLK[1:0]
Description
Reserved
Medium low drive strength (2X) for LLC1 up to 55 MHz
Medium high drive strength (3X) for LLC1 from 55 MHz to 105 MHz
High drive strength (4X) for LLC1 >100 MHz
for the drive strength control of the pixel bus,
for the drive strength controls of the pixel bus,
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ADV7604