Ppi Clock Select Switch (Sw5); Test Dip Switches (Sw10 And Sw11); Audio Enable Switch (Sw12) - Analog Devices ADSP-BF561 EZ-KIT Lite Manual

PPI Clock Select Switch (SW5)

The switch controls a clock selection of the PPI interfaces as described
SW5
in Table 2-7 and
Table 2-7. PPICLK1 Clock Source Setup
SW5 Position 1
PPI0_CKSEL0
ON
OFF
X
Table 2-8. PPICLK2 Clock Source Setup
SW5 Position 3
PPI1_CKSEL0
ON
OFF
X

Test DIP Switches (SW10 and SW11)

Two DIP switches (
board. The switches are used only for testing and should remain in the
position.

Audio Enable Switch (SW12)

The audio enable switch (
processor. The default is all positions
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
www.BDTIC.com/ADI
ADSP-BF561 EZ-KIT Lite Hardware Reference
Table 2-8.
SW5 Position 2
PPI0_CKSEL1
ON
ON
OFF
SW5 Position 4
PPI1_CKSEL1
ON
ON
OFF
and ) are located on the bottom of the
SW10 SW11
) disconnects the audio signals from the
SW12
PPIxCLK1 Source
27 MHz oscillator (default)
ADV7183 clock out
Expansion interface
PPICLK2 Source
27 MHz oscillator (default)
ADV7183 clock out
Expansion interface
.
ON
OFF
2-13