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Data Cache Control Instructions
The processor defines three data cache control instructions that are acces-
sible in User and Supervisor modes. The instructions are
and
. Examples of each of these instructions can be found in
FLUSHINV
Chapter 17, "Cache Control."
•
PREFETCH
L1 cache. If the prefetch hits in the cache, generates an exception,
or addresses a cache inhibited region,
. It can be used to begin a data fetch prior to when the processor
NOP
needs the data, to improve performance.
•
(Data Cache Flush) causes the data cache to synchronize the
FLUSH
specified cache line with external memory. If the cached data line is
dirty, the instruction writes the line out and marks the line clean in
the data cache. If the specified data cache line is already clean or
does not exist,
•
FLUSHINV
cache to perform the same function as the
then invalidate the specified line in the cache. If the line is in the
cache and dirty, the cache line is written out to external memory.
The Valid bit in the cache line is then cleared. If the line is not in
the cache,
If software requires synchronization with system hardware, place an
instruction after the
has completed. If ordering is desired to ensure that previous stores have
been pushed through all the queues, place an
.
FLUSH
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
(Data Cache Prefetch) attempts to allocate a line into the
functions like a
FLUSH
(Data Cache Line Flush and Invalidate) causes the data
functions like a
FLUSHINV
instruction to ensure that the flush operation
FLUSH
PREFETCH
functions like a
PREFETCH
.
NOP
instruction and
FLUSH
.
NOP
instruction before the
SSYNC
Memory
,
,
FLUSH
SSYNC
6-37
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