Data Memory Interface; External Data Memory Read/Write - Analog Devices adsp-2100 Manual

10 Memory Interface
10.3
This section describes the data memory interface of all ADSP-21xx
processors except the ADSP-2181.
The processors supply a 14-bit address on the data memory address bus
(DMA) which is multiplexed off-chip. Data is transferred across the upper
16 bits of the 24-bit memory data bus, which is also multiplexed off-chip.
A data memory select pin,
driven with a data memory address and memory can be selected.
Two control lines indicate the direction of the transfer. Memory read (
is active low signaling a read and memory write (
write operation. Typically, you would connect
to
RD
10.3.1
Internal data memory accesses are transparent to the external memory
interface. Only off-chip accesses drive the memory interface. Off-chip data
memory accesses follow the same sequence as off-chip program memory
accesses, namely:
1. The processor places the address on the DMA bus, which is
multiplexed off-chip, and
RD
2.
3. Within a specified time, data is placed on the data bus, multiplexed to
the internal DMD bus.
4. The data is read or written and
DMS
5.
The basic read and write cycles are illustrated in Figure 10.2.
For a dual off-chip data fetch, the data from program memory is read first,
then the data memory data.
10 – 10

DATA MEMORY INTERFACE

(Output Enable) and
OE

External Data Memory Read/Write

WR
or is asserted.
is deasserted.
, indicates that the address bus is being
DMS
to (Write Enable) of your memory.
WR WE
DMS
is asserted.
RD WR
(or
) is active low for a
WR
to (Chip Enable),
DMS CE
) is deasserted.
)
RD