Standard Dsp Serial Mode Control Bits; Clocking Options; Frame Sync Options - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Standard DSP Serial Mode Control Bits

Several bits in the
DSP serial mode operation:
• Operation mode, master mode enable (
• Word length (
• SPORT enable (

Clocking Options

In standard DSP serial mode, the SPORTs can either accept an external
serial clock or generate it internally. The
determines the selection of these options (see
page 5-36 for more details). For internally-generated serial clocks, the
bits in the
CLKDIV
Figure 5-10 on page 5-70
Finally, programs can select whether the serial clock edge is used for sam-
pling or driving serial data and/or frame syncs. This selection is performed
using the
CKRE
more details).

Frame Sync Options

A variety of framing options are available for the SPORTs. For detailed
descriptions of framing options, see
In this mode, these options are independent of clocking, data formatting,
or other configurations. The frame sync signal (
framing signal for serial word transfers.
Framing is optional for serial communications. The
register controls whether the frame sync signal is required for every serial
word transfer or if it is used simply to start a block of serial word transfers.
See "Framed Versus Unframed Frame Syncs" on page 5-37
ADSP-21368 SHARC Processor Hardware Reference
control register enable and configure standard
SPCTLx
)
SLEN
and
SPEN_A
register configure the serial clock rate (see
DIVx
for more details).
bit in the register (see
SPCTL
)
OPMODE
)
SPEN_B
bit in the
ICLK
"Clock Signal Options" on
Table A-8 on page A-37
"Frame Sync Options" on page
SPORTx_FS
FSR
Serial Ports
register
SPCTL
for
5-37.
) is used as a
bit in the
SPCTL
for more
5-13