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• Internal clock enable (
• Word length (
• Channel enable (
Clocking Options
In standard serial mode, the serial portscan either accept an external serial
clock or generate it internally. The
mines the selection of these options. For internally-generated serial clocks,
the
bits in the
CLKDIV
Finally, programs can select whether the serial clock edge is used for sam-
pling or driving serial data and/or frame syncs. This selection is performed
using the
bit in the
CKRE
ters (SPCTLx)" on page A-30
Frame Sync Options
A variety of framing options are availabl e for the serial ports. In this mode,
the options are independent of clocking, data formatting, or other config-
urations. The frame sync signal (
serial word transfers.
Framing is optional for serial communications. The
register controls whether the frame sync signal is required for every serial
word transfer or if it isused simply to start a block of serial word transfers.
Similar to the serial clock, the frame sync can be an external signal or gen-
erated internally. The
between these options.
For internally-generated frame syncs, the
configure the frame sync rate. For internally-generated frame syncs, it is
also possible to configure whether the frame sync signal is activated based
on the
setting and the transmit or receive buffer status, or by the
FSDIV
setting only. All settings are configured through the
FSDIV
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
)
ICLK
, 3–32 bits)
SLEN
or
SPEN_A
SPEN_B
ICLK
register configure the serial clock rate.
DIVx
register. See
SPCTL
for more details.
SPORTx_FS
bit in the
IFS
SPCTL
)
bit in the
register deter-
SPCTL
"SPORT Serial Control Regis-
) is used as a framing signal for
bit in the
FSR
register allows the selection
bits in the
FSDIV
DIVx
DIFS
Serial Ports
SPCTL
registers
bit of the
6-35
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