Clocking And Sampling Rates; Core Clock; Sampling Rates - Analog Devices ADAU1961 Manual

ADAU1961

CLOCKING AND SAMPLING RATES

R1: PLL CONTROL REGISTER
MCLK ÷ X

CORE CLOCK

Clocks for the converters and the serial ports are derived from
the core clock. The core clock can be derived directly from
MCLK or it can be generated by the PLL. The CLKSRC bit (Bit
3 in Register R0, Address 0x4000) determines the clock source.
The INFREQ[1:0] bits should be set according to the expected
input clock rate selected by CLKSRC; this value also determines
the core clock rate and the base sampling frequency, f
For example, if the input to CLKSRC = 49.152 MHz (from
PLL), then
INFREQ[1:0] = 1024 × f
f = 49.152 MHz/1024 = 48 kHz
S
The PLL output clock rate is always 1024 × f
control register automatically sets the INFREQ[1:0] bits to
1024 × f when using the PLL. When using a direct clock, the
S
INFREQ[1:0] frequency should be set according to the MCLK
pin clock rate and the desired base sampling frequency.
Table 11. Clock Control Register (Register R0, Address 0x4000)
Bits Bit Name
3 CLKSRC
[2:1] INFREQ[1:0]
0 COREN
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R0: CLOCK
CONTROL REGISTER
× (R + N/M)
INFREQ[1:0]
f
256 ×
f
768 ×
CLKSRC
.
S
S
, and the clock
S
Settings
0: Direct from MCLK pin (default)
1: PLL clock
00: 256 × f (default)
S
01: 512 × f
S
10: 768 × f
S
11: 1024 × f
S
0: Core clock disabled (default)
1: Core clock enabled
R17: CONVERTER
CONTROL 0 REGISTER
CORE
CLOCK CONVSR[2:0]
f
, 512 × , f
/0.5, 1, 1.5, 2, 3, 4, 6
S S
S
f
, 1024 ×
S S
Figure 29. Clock Tree Diagram

SAMPLING RATES

The ADCs, DACs, and serial port share a common sampling
rate that is set in Register R17 (Converter Control 0 register,
Address 0x4017). The CONVSR[2:0] bits set the sampling rate
as a ratio of the base sampling frequency.
Table 12 and Table 13 list the sampling rate divisions for
common base sampling rates.
Table 12. 48 kHz Base Sampling Rate Divisions
Base Sampling
Frequency
f = 48 kHz
S
Table 13. 44.1 kHz Base Sampling Rate Divisions
Base Sampling
Frequency
f = 44.1 kHz
S
Rev. 0 | Page 24 of 76
SERIAL DATA
ADCs DACs
INPUT/OUTPUT
Sampling Rate Scaling Sampling Rate
f /1 48 kHz
S
f /6 8 kHz
S
f /4 12 kHz
S
f /3 16 kHz
S
f /2 24 kHz
S
f /1.5 32 kHz
S
f /0.5 96 kHz
S
Sampling Rate Scaling Sampling Rate
f /1 44.1 kHz
S
f /6 7.35 kHz
S
f /4 11.025 kHz
S
f /3 14.7 kHz
S
f /2 22.05 kHz
S
f /1.5 29.4 kHz
S
f /0.5 88.2 kHz
S
PORT