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HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
THEORY OF OPERATION
The FIFO evaluation board can be divided into several circuits,
each of which plays an important part in acquiring digital data
from the ADC and allows the PC to upload and process that
data. The evaluation kit is based around the IDT72V283 FIFO
chip from IDT. The system can acquire digital data at speeds up
to 133 MSPS and data record lengths up to 32 kB using the
HSC-ADC-EVALA-SC FIFO evaluation kit. The HSC-ADC-
EVALA-DC, which has two FIFO chips, is available to evaluate
dual ADCs or demultiplexed data from ADCs sampling faster
than 133 MSPS. A USB 2.0 microcontroller communicating
with ADC Analyzer allows for easy interfacing to newer
computers using the USB 2.0 (USB 1.1 compatible) interface.
The process of filling the FIFO chip(s) and reading the data
back requires several steps. First, ADC Analyzer initiates the
FIFO chip(s) fill process. The FIFO chip(s) are reset using a
master reset signal (MRS). The USB Microcontroller then is
suspended, which turns off the USB oscillator, ensuring that it
does not add noise to the ADC input. After the FIFO chip(s)
completely fill, the full flags from the FIFO chip(s) send a signal
to the USB microcontroller to wake up the microcontroller
from suspend. ADC Analyzer waits for approximately 30 ms
and begins the readback process.
During the readback process, the acquisition of data from
FIFO 1 (U201) or FIFO 2 (U101) is controlled via the signals
OEA and OEB. Because the data outputs of both FIFO chips
drive the same 16-bit data bus, the USB microcontroller
controls the OEA and OEB signals to read data from the correct
FIFO chip. From an application standpoint, ADC Analyzer
sends commands to the USB microcontroller to initiate a read
from the correct FIFO chip, or both FIFO chips in dual or
interleaved mode.
CLOCKING DESCRIPTION
Each channel of the buffer memory requires a clock signal to
capture data. These clock signals are normally provided by the
ADC evaluation board and are passed along with the data
through Connector J104/204 (Pin 37 for both Channel 1 and
Channel 2). If only a single clock is passed for both channels,
they can be connected together by Jumper J303.
Jumpers J304 and J305 at the output of the LVDS receiver allow
the output clock to be inverted by the LVDS receiver. By default,
the clock outputs are inverted by the LVDS receiver.
The single-ended clock signal from each data channel is
buffered and converted to a differential CMOS signal by two
gates of a low voltage differential signal (LVDS) receiver, U301.
This allows the clock source for each channel to be CMOS, TTL,
or ECL. The clock signals are ac-coupled by 0.1 µF capacitors.
Potentiometers R312 and R315 allow for fine tuning the
threshold of the LVDS gates. In applications where fine-tuning
the threshold is critical, these potentiometers may be replaced
with a higher resistance value to increase the adjustment range.
Resistors R303, R304, R307, R308, R311, R313, R314, and R316
set the static input to each of the differential gates to a dc
voltage of approximately 1.5 V.
At assembly, solder Jumpers J310–J313 are set to bypass the
potentiometer. For fine adjustment using the pot, the solder
jumpers must be removed.
U302, an XOR gate array, is included in the design to let users
add gate delays to the FIFO memory chips clock paths. They are
not required under normal conditions and are bypassed at
assembly by Jumpers J314 and J315. Jumpers J306 and J307
allow the clock signals to be inverted through an XOR gate. In
the default setting, the clocks are not inverted by the XOR gate.
The clock paths described above determine the WRT_CLK1
and WRT_CLK2 signals at each FIFO memory chip (U101 and
U201, Pin 80). The timing options above should let you choose
a clock signal that meets the setup and hold time requirements
to capture valid data.
A clock generator can be applied directly to S1 and/or S3. This
clock generator should be the same unit that provides the clock
for the ADC. These clock paths are ac-coupled, so that a sine
wave generator can be used. DC bias can be adjusted by
R301/R302 and R305/R306. Note that J301 and J302 (SMA
connectors) and R301, R302, R305, and R306 are not installed at
the factory and must be installed by the user.
The DS90LV048A differential line receiver is used to square the
clock signal levels applied externally to the FIFO evaluation
board. The output of this clock receiver can either directly drive
the write clock of the IDT72V283 FIFO(s), or first pass through
the XOR gate timing circuitry described above.
CLOCKING WITH INTERLEAVED DATA
ADCs with very high data rates may exceed the capability of a
single buffer memory channel (~133 MSPS). These converters
often demultiplex the data into two channels to reduce the rate
required to capture the data. In these applications, ADC
Analyzer must interleave the data from both channels to
process it as a single channel. The user can configure the
software to process the first sample from Channel 1, the second
from Channel 2, and so on, or vice versa, (see the
Troubleshooting section for more information). The
synchronization circuit included in the buffer memory forces a
small delay between the write enable signals (WENA and
WENB) to the FIFO memory chips (Pin 1, U101 and U201),
ensuring that the data is captured in one FIFO before the other.
Jumpers J401 and J402 determine which FIFO receives WENA
and which FIFO receives WENB
Rev. 0 | Page 10 of 44
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