Packing Mode 00; Clocking Edge Selection - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Clocking Edge Selection

Notice that in all four packing modes described, data is read on a clock
edge, but the specific edge used (rising or falling) is not indicated. Clock
edge selection is configurable using the
the
IDP_PDAP_CTL
latched on the falling edge. Clearing this bit (= 0) causes data to be latched
on the rising edge (default).
Hold Input
A synchronous clock enable can be passed from any DAI pin to the PDAP
packing unit. This signal is called

The
PDAP_HOLD
the frame sync for IDP channel 0. Its functionality is determined
by the PDAP Enable bit (
When the
PDAP_HOLD
and no new data is read from the input pins. The packing unit operates as
normal, but it pauses and waits for the
and waits for the correct number of distinct input samples before passing
the packed data to the FIFO.
Figure 11-8 shows the affect of the hold input (B) for four 8-bit words in
Packing Mode 00, and
for two 16-bit words in Packing Mode 10.
ADSP-2126x SHARC Processor Hardware Reference
register). Setting this bit (= 1) causes the data to be
PDAP_HOLD
signal is actually the same physical internal signal as
IDP_PDAP_EN
signal is , all latching clock edges are ignored
HIGH
Figure 11-9 shows the affect of the hold input (B)
Input Data Port
IDP_PDAP_CLKEDGE
.
).
signal to be deasserted
PDAP_HOLD
bit (bit 29 of
11-11