Mpu Standby And Event Interfaces; Fpga-To-Hps Interrupts; General-Purpose Interfaces - Altera Cyclone V Device Handbook

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MPU Standby and Event Interfaces

MPU Standby and Event Interfaces
MPU standby and event signals are notification signals to the FPGA fabric that the MPU is in standby. Event
signals are used to wake up the Cortex-A9 processors from a wait for event (WFE) state. The standby and
event signals are included in the following interfaces:
• h2f_mpu_events MPU standby and event interface, including the following signals:
• h2f_mpu_eventi Sends an event from logic in the FPGA fabric to the MPU. This FPGA-to-HPS
signal is used to wake up a processor that is in a Wait For Event state. Asserting this signal has the same
effect as executing the SEV instruction in the Cortex-A9. This signal must be de-asserted until the FPGA
fabric is powered-up and configured.
• h2f_mpu_evento Sends an event from the MPU to logic in the FPGA fabric. This HPS-to-FPGA
signal is asserted when an SEV instruction is executed by one of the Cortex-A9 processors.
• h2f_mpu_standbywfe[1:0] Indicates whether each Cortex-A9 processor is in the WFE state
• h2f_mpu_standbywfi[1:0] Indicates whether each Cortex-A9 processor is in the wait for
interrupt (WFI) state
• h2f_mpu_gp General purpose interface
The MPU provides signals to indicate when it is in a standby state. These signals are available to custom
hardware designs in the FPGA fabric.
Related Information
Cortex-A9 MPCore
For more information, refer to Cortex-A9 MPU Subsystem.

FPGA-to-HPS Interrupts

You can configure the HPS component to provide 64 general-purpose FPGA-to-HPS interrupts, allowing
soft IP in the FPGA fabric to trigger interrupts to the MPU's generic interrupt controller (GIC). The interrupts
are implemented through the following 32-bit interfaces:
• f2h_irq0 FPGA-to-HPS interrupts 0 through 31
• f2h_irq1 FPGA-to-HPS interrupts 32 through 63
The FPGA-to-HPS interrupts are asynchronous on the FPGA interface. Inside the HPS, the interrupts are
synchronized to the MPU's internal peripheral clock (periphclk).

General-Purpose Interfaces

You can use the FPGA manager to supply the h2f_mpu_gp interface, which includes the following general-
purpose signals:
• 32 FPGA-to-HPS signals
• 32 HPS-to-FPGA signals
Related Information
FPGA Manager
For more information, refer to FPGA Manager.
Altera Corporation
on page 6-4
on page 13-1
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2013.12.30
HPS Component Interfaces
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