Lightweight Hps-To-Fpga Axi Master Interface; Fpga-To-Hps Sdram Interface; Hps-To-Fpga Mpu General Purpose I/O Interface - Altera Cyclone V Device Handbook

cv_54030
2013.12.30
Related Information
• Memory-Mapped Interfaces
• Mentor Verification IP Altera Edition User Guide

Lightweight HPS-to-FPGA AXI Master Interface

The lightweight HPS-to-FPGA AXI master interface, h2f_lw_axi_master, is connected to a Mentor
Graphics AXI master BFM for simulation. Qsys configures the BFM as shown in the following table. The
BFM clock input is connected to h2f_lw_axi_clock clock.
Table 29-7: Configuration of Lightweight HPS-to-FPGA AXI Master BFM
AXI Address Width
AXI Read and Write Data Width
AXI ID Width
You control and monitor the AXI master BFM by using the BFM API.
Related Information
• Memory-Mapped Interfaces
• Mentor Verification IP Altera Edition User Guide

FPGA-to-HPS SDRAM Interface

The HPS component contains a memory interface simulation model to which all of the FPGA-to-HPS
SDRAM interfaces are connected. The model is based on the HPS implementation and provides cycle-level
accuracy, reflecting the true bandwidth and latency of the interface. However, the model does not have the
detailed configuration provided by the HPS software, and hence does not reflect any inter-port scheduling
that might occur under contention on the real hardware when different priorities or weights are used.
Related Information
Functional Description Hard Memory Interface
For more information, refer to "EMI-Related HPS Features in SoC Devices" in the Functional
Description—Hard Memory Interface chapter in volume 3 of the External Memory Interface Handbook.

HPS-to-FPGA MPU General Purpose I/O Interface

The HPS-to-FPGA MPU general-purpose I/O interface is connected to an Altera conduit BFM for simulation.
The following table lists the name of each interface, along with API function names for each type of simulation.
You can monitor the interface state changes or set the interface by using the API listed.
HPS Simulation Support
Send Feedback
on page 28-2
Parameter
on page 28-2
Lightweight HPS-to-FPGA AXI Master Interface
21
32
12
Value
Altera Corporation
29-5