Transmitter Channel Datapath; Tx Phase Compensation Fifo; Byte Serializer - Altera Cyclone IV Device Handbook

Chapter 1: Cyclone IV Transceivers Architecture

Transmitter Channel Datapath

Transmitter Channel Datapath
The following sections describe the Cyclone IV GX transmitter channel datapath
architecture as shown in
■
■
■
■
■

TX Phase Compensation FIFO

The TX phase compensation FIFO compensates for the phase difference between the
low-speed parallel clock and the FPGA fabric interface clock, when interfacing the
transmitter channel to the FPGA fabric (directly or through the PIPE and
PCIe hard IP). The FIFO is four words deep, with latency between two to three
parallel clock cycles.
diagram.
Figure 1–4. TX Phase Compensation FIFO Block Diagram
Note to
(1) The x refers to the supported 8-, 10-, 16-, or 20-bits transceiver channel width.
1
The FIFO can operate in registered mode, contributing to only one parallel clock cycle
of latency in Deterministic Latency functional mode. For more information, refer to
"Deterministic Latency Mode" on page
f
For more information about FIFO clocking, refer to
Interface Clocking" on page

Byte Serializer

The byte serializer divides the input datapath width by two to allow transmitter
channel operation at higher data rates while meeting the maximum FPGA fabric
frequency limit. This module is required in configurations that exceed the maximum
FPGA fabric-transceiver interface clock frequency limit and optional in configurations
that do not.
f
For the FPGA fabric-transceiver interface frequency specifications, refer to the
IV Device Data
February 2015 Altera Corporation
Figure
TX Phase Compensation FIFO
Byte Serializer
8B/10B Encoder
Serializer
Transmitter Output Buffer
Figure 1–4
tx_datain[x..0] (1)
Figure 1–4:
1–43.
Sheet.
1–3:
shows the TX phase compensation FIFO block
TX Phase
Compensation
FIFO
wr_clk rd_clk
1–73.
"FPGA Fabric-Transceiver
tx_phase_comp_fifo_error
Data output to
the byte serializer
or the 8B/10B encoder
Cyclone
Cyclone IV Device Handbook,
Volume 2
1–5