Configuration; High-Speed Transceivers (Cyclone Iv Gx Devices Only) - Altera Cyclone IV Device Handbook

1–10
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For more information, refer to the
chapter.

Configuration

Cyclone IV devices use SRAM cells to store configuration data. Configuration data is
downloaded to the Cyclone IV device each time the device powers up. Low-cost
configuration options include the Altera EPCS family serial flash devices and
commodity parallel flash configuration options. These options provide the flexibility
for general-purpose applications and the ability to meet specific configuration and
wake-up time requirements of the applications.
Table 1–9
Table 1–9. Configuration Schemes for Cyclone IV Device Family
Cyclone IV GX
Cyclone IV E
Note to
(1) The FPP configuration scheme is only supported by the EP4CGX30F484 and EP4CGX50/75/110/150 devices.
IEEE 1149.6 (AC JTAG) is supported on all transceiver I/O pins. All other pins
support IEEE 1149.1 (JTAG) for boundary scan testing.
f
For more information, refer to the
chapter.
For Cyclone IV GX devices to meet the PCIe 100 ms wake-up time requirement, you
must use passive serial (PS) configuration mode for the EP4CGX15/22/30 devices
and use fast passive parallel (FPP) configuration mode for the EP4CGX30F484 and
EP4CGX50/75/110/150 devices.
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For more information, refer to the
Cyclone IV Devices
The cyclical redundancy check (CRC) error detection feature during user mode is
supported in all Cyclone IV GX devices. For Cyclone IV E devices, this feature is only
supported for the devices with the core voltage of 1.2 V.
f
For more information about CRC error detection, refer to the
Cyclone IV Devices

High-Speed Transceivers (Cyclone IV GX Devices Only)

Cyclone IV GX devices contain up to eight full duplex high-speed transceivers that
can operate independently. These blocks support multiple industry-standard
communication protocols, as well as Basic mode, which you can use to implement
your own proprietary protocols. Each transceiver channel has its own pre-emphasis
and equalization circuitry, which you can set at compile time to optimize signal
integrity and reduce bit error rates. Transceiver blocks also support dynamic
reconfiguration, allowing you to change data rates and protocols on-the-fly.
Cyclone IV Device Handbook,
Volume 1
lists which configuration schemes are supported by Cyclone IV devices.
Devices
Table 1–9:
chapter.
chapter.
Chapter 1: Cyclone IV FPGA Device Family Overview
External Memory Interfaces in Cyclone IV Devices
Supported Configuration Scheme
AS, PS, JTAG, and FPP
AS, AP, PS, FPP, and JTAG
JTAG Boundary-Scan Testing for Cyclone IV Devices
Configuration and Remote System Upgrades in
Cyclone IV Device Family Architecture
(1)
SEU Mitigation in
March 2016 Altera Corporation