Pin Configuration And Function Descriptions - Analog Devices AD9866 Instructions Manual

AD9866

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 9. Pin Function Descriptions
Pin No.
1
2 to 5
6
7
8, 9
10
11
12
13
14
15
64 63 62
ADIO11/Tx[5]
1
ADIO10/Tx[4]
2
PIN 1
ADIO9/Tx[3]
3
IDENTIFIER
ADIO8/Tx[2] 4
ADIO7/Tx[1] 5
ADIO6/Tx[0] 6
ADIO5/Rx[5]
7
ADIO4/Rx[4] 8
ADIO3/Rx[3]
9
ADIO2/Rx[2]
10
11
ADIO1/Rx[1]
ADIO0/Rx[0]
12
RXEN/RXSYNC
13
TXEN/TXSYNC
14
TXCLK/TXQUIET 15
RXCLK
16
17 18 19
Mnemonic Mode
ADIO11 HD
Tx[5] FD
ADIO10 to 7 HD
Tx[4 to 1] FD
ADIO6 HD
Tx[0] FD
ADIO5 HD
Rx[5] FD
ADIO4, 3 HD
Rx[4, 3] FD
ADIO2 HD
Rx[2] FD
ADIO1 HD
Rx[1] FD
ADIO0 HD
Rx[0] FD
RXEN HD
RXSYNC FD
TXEN HD
TXSYNC FD
TXCLK HD
TXQUIET FD
61 60 59 58 57 56 55 54 53
52
AD9866
TOP VIEW
(Not to Scale)
20 21 22 23 24 25 26 27 28
29
Figure 2. Pin Configuration
1
Description
MSB of ADIO Buffer
MSB of Tx Nibble Input
Bits 10 to 7 of ADIO Buffer
Bits 4 to 1 of Tx Nibble Input
Bit 6 of ADIO Buffer
LSB of Tx Nibble Input
Bit 5 of ADIO Buffer
MSB of Rx Nibble Output
Bits 4 to 3 of ADIO Buffer
Bits 4 to 3 of Rx Nibble Output
Bit 2 of ADIO Buffer
Bit 2 of Rx Nibble Output
Bit 1 of ADIO Buffer
Bit 1 of Rx Nibble Output
LSB of ADIO Buffer
LSB of Rx Nibble Output
ADIO Buffer Control Input
Rx Data Synchronization Output
Tx Path Enable Input
Tx Data Synchronization Input
ADIO Sample Clock Input
Fast TxDAC/IAMP Power-Down
Rev. A | Page 10 of 48
51 50 49
AVSS
48
AVSS
47
IOUT_N–
46
45 IOUT_G–
44 AVSS
43 AVDD
REFIO
42
REFADJ
41
40 AVDD
39 AVSS
38 RX+
37 RX–
AVSS
36
AVDD
35
34 AVSS
REFT
33
30 31 32