Pin Configuration And Function Descriptions - Analog Devices ADF7021-V Manual

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 8. Pin Function Descriptions
Pin No. Mnemonic
1 VCOIN
2 CREG1
3 VDD1
4 RFOUT
5 RFGND
6 RFIN
7 RFIN
8 R
LNA
9 VDD4
10 RSET
11 CREG4
12, 19, 22 GND4
13 to 16
MIX_I, MIX_I,
MIX_Q, MIX_Q
17, 18, 20, FILT_I, FILT_I,
21
FILT_Q, FILT_Q,
23 TEST_A
24 CE
25 SLE
26 SDATA
PIN 1
VCOIN 1
INDICATOR
2
CREG1
VDD1 3
RFOUT 4
RFGND 5
ADF7021-V
RFIN 6
7
RFIN
(Not to Scale)
R
8
LNA
VDD4 9
RSET 10
11
CREG4
GND4 12
NOTES
1. THE EXPOSED PADDLE MUST BE CONNECTED
TO THE GROUND PLANE.
Figure 10. Pin Configuration
Description
Do not connect.
Regulator Voltage for PA Block. Place a series 3.9 Ω resistor and a 100 nF capacitor between this pin and
ground for regulator stability and noise rejection.
Voltage Supply for PA Block. Place decoupling capacitors of 0.1 μF and 100 pF as close as possible to this
pin. Tie all VDDx pins together.
The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. The
output should be impedance matched to the desired load using suitable components.
Ground for Output Stage of Transmitter. Tie all GND pins together.
LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer.
Complementary LNA Input.
External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
Voltage Supply for LNA/Mixer Block. Decouple this pin to ground with a 10 nF capacitor. Tie all VDDx pins
together.
External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ resistor with
5% tolerance.
Regulator Voltage for LNA/Mixer Block. Place a 100 nF capacitor between this pin and ground for
regulator stability and noise rejection.
Ground for LNA/Mixer Block. Tie all GND pins together.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
Signal Chain Test Pin. This pin is high impedance under normal conditions and should be left unconnected.
Chip Enable. Bringing CE low puts the ADF7021-V into complete power-down. Register values are lost
when CE is low, and the part must be reprogrammed after CE is brought high.
Load Enable, CMOS Input. When SLE goes high, the data stored in the shift registers is loaded into one of
the 16 latches. A latch is selected using the control bits.
Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This pin is a
high impedance CMOS input.
Rev. 0 | Page 15 of 60
CLKOUT
36
TxRxCLK
35
34 TxRxDATA
33 SWD
VDD2
32
31 CREG2
TOP VIEW
ADCIN
30
GND2
29
SCLK
28
SREAD
27
26 SDATA
SLE
25
ADF7021-V