Interrupting Idle; Summary - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Interrupting IDLE

The sequencer supports placing the DSP in
that halts the processor core in a low power state. The halt occurs until
any interrupt is latched, serviced, and then returned from using the
instruction. When executing an
one more instruction at the current fetch address and then suspends oper-
ation. The DSP's I/O processor is not affected by the
DMA transfers to or from internal memory continue uninterrupted. The
processor's internal clock and timer (if enabled) continue to run during
. When an interrupt occurs, the processor responds normally. After
IDLE
two cycles used to fetch and decode the first instruction of the interrupt
service routine, the processor continues executing instructions normally.

Summary

To manage events, the sequencer's interrupt controller handles interrupt
processing, determines whether an interrupt is masked, and generates the
appropriate interrupt vector address.
With selective caching, the instruction cache lets the DSP access data in
program memory and fetch an instruction (from the cache) in the same
cycle. The DAG2 data address generator outputs program memory data
addresses.
The sequencer evaluates conditional instructions and loop termination
conditions by using information from the status registers. The loop
address stack and loop counter stack support nested loops. The status
stack stores status registers for implementing nested interrupt routines.
Figure 3-6 identifies all the functional blocks and their relationship to one
another in detail.
ADSP-2126x SHARC Processor Hardware Reference
Program Sequencer
—a special instruction
IDLE
instruction, the sequencer fetches
IDLE
RTI
instruction—
IDLE
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