External I/O Device To External Memory (Flyby) - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Table 7-7. Internal Memory TCB
Transmitter TCB Configuration
Register Field
DI
DX
DY
DP TY
DP PR
DP 2DDMA
DP LEN
DP INT
DP DRQ
DP CHEN
DP CHTG
DP CHPT

External I/O Device to External Memory (Flyby)

Consider the case where the transfer direction is from an external I/O
device to the external memory. There is no internal memory access. The
configurations for transmitter and receiver
on page 7-57 and Table 7-10 on page 7-58 respectively.
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Description
Internal memory address
Number of words to transfer and address modifier. The
to X dimension data when the
Number of Y dimension words to transfer and address modifier when the
bit is set in the
2DDMA DP
Internal memory
Channel priority
1 – Increases the channel priority – internal bus DMA request
priority is high.
Sets the two-dimensional DMA mode
1 – Enables two-dimensional DMA mode; the
(See "Two-Dimensional DMA" on page 7-45.)
Can be word, double word, or quad-word. Note the lowest internal bus utili-
zation is achieved with quad-words.
Sets interrupt
1 – Interrupts the core once the complete block is transferred.
Sets transfer mode
1 – Transfers each data item per request.
Sets chaining mode
1 – Enables chaining.
Defines register to be loaded; must be the same channel.
TCB
Chaining pointer – relevant when chaining is enabled.
Direct Memory Access
bit is set in the
2DDMA
register; otherwise irrelevant.
DY
s are described in Table 7-9
TCB
register also refers
DX
register.
DP
register becomes relevant.
7-55