Table of Contents
Advertisement
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
JUMPERS
Use the legends below to configure the jumpers. On the FIFO evaluation board, Channel 1 is associated with the bottom IDT FIFO chip,
and Channel 2 is associated with the top IDT FIFO chip (closest to the Analog Devices logo).
Table 2. Jumper Legend
Position
In
Out
Position 1 or Position 3
Table 3 Solder Bridge Legend
Position
In
Out
DEFAULT SETTINGS
Table 4 lists the default settings for each model of the FIFO Evaluation Kit. The single channel (SC) model is configured to work with a
single channel ADC using the bottom FIFO, U201. The dual channel (DC) model is configured to work with demultiplexed ADCs (such
as the AD9430). Dual channel ADC settings are shown in a separate column, as are settings for the opposite (top) FIFO, U101 for a single
channel ADC. To align the timing properly, some evaluation boards may require modifications to these settings. Refer to the Clocking
Description section in the Theory of Operation section for more information.
Another useful way to configure the jumper settings easily for various configurations is to consult ADC Analyzer under the Help > About
HSC_ADC_EVALA, and click Setup Default Jumper Wizard. Then click the configuration setting that applies to the application of
interest. A picture of the FIFO board is displayed for that application with a visual of the correct jumper settings already in place.
Table 4. Jumper Configurations
Single
Channel
Settings,
Default
Jumper
No.
(Bottom)
J101
Out
J102
Out
J103
In
J105
In
J106
Out
J107
Out
J201
Out
J202
Out
J203
In
J205
In
J206
Out
J207
Out
J303
In
J304
Position 3
J305
Position 3
J306
Out
J307
Out
J310-13
In
J314
Position 3
J315
Position 1
J401
Position 1
Description
Jumper in place (2-pin header)
Jumper removed (2-pin header)
Denotes the position of a 3-pin header. Position 1 is marked on the board.
Description
Solder pads should be connected
Solder pads should not be connected
Dual
Demultiplexed
Channel
Settings
Settings
Out
Out
Out
Out
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
Out
Out
Out
Out
Out
Out
Position 3
Position 3
Position 3
Position 3
Out
Out
Out
Out
In
In
Position 3
Position 3
Position 1
Position 1
Position 1
Position 1
Single
Channel
Settings
1
(Top)
Description
Out
Not Used
Out
Not Used
In
Ground Unused Pins from Input Header
In
Ground Unused Pins from Input Header
Out
Not Used
Out
Not Used
Out
Not Used
Out
Not Used
In
Takes the FF Signal on FIFO1 out of the Circuit
In
Takes the EF Signal on FIFO1 out of the Circuit
Out
Not Used
Out
Not Used
In
OUT for Interleave and Dual/Ties Write Clocks Together
Position 3
POS3: Invert Clock out of DS90
Position 3
POS3: Invert Clock out of DS90
Out
NO Invert from XOR (U302)
Out
NO Invert from XOR (U302)
In
All Solder Jumpers are Shorted
Position 3
No Timing Delay
Position 1
No Timing Delay
Position 1
WEN Select
Rev. 0 | Page 26 of 44
Advertisement
Table of Contents
