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Analog Devices ADSP-219 Series Hardware Reference Manual
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Analog Devices ADSP-219 Series Hardware Reference Manual

Analog Devices ADSP-219 Series Hardware Reference Manual

Dsp peripheral registers
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B ADSP-2192 DSP PERIPHERAL
REGISTERS
Figure B-0.
Table B-0.
Listing B-0.
Overview
The DSP has general-purpose and dedicated registers in each of its func-
tional blocks. The register reference information for each functional block
includes bit definitions, initialization values, and (for I/O processor regis-
ters) memory-mapped addresses. Information on each type of register is
available at the following locations:
•
"Core Status Registers" on page A-8
•
"Computational Unit Registers" on page A-16
•
"Program Sequencer Registers" on page A-19
•
"Data Address Generator Registers" on page A-26
•
"Peripheral Registers" on page B-2
When writing DSP programs, it is often necessary to set, clear, or test bits
in the DSP's registers. While these bit operations can be done by referring
to the bit's location within a register or (for some operations) the register's
address with a hexadecimal number, it is much easier to use symbols that
correspond to the bit's or register's name.
For convenience and consistency, Analog Devices provides header files
that define these bit and register definitions (def2192_IO.h,
def2192_PCI.h, def2192_USB.h, def2192-12.h, and def219x.h). Note
that the def2192-12.h file also contains the definitions from the IO, PCI,
and USB header files.
ADSP-219x/2192 DSP Hardware Reference
B-1

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Summary of Contents for Analog Devices ADSP-219 Series

  • Page 1 For convenience and consistency, Analog Devices provides header files that define these bit and register definitions (def2192_IO.h, def2192_PCI.h, def2192_USB.h, def2192-12.h, and def219x.h). Note that the def2192-12.h file also contains the definitions from the IO, PCI,...
  • Page 2 Peripheral Registers A sample of def219x.h is shown in “Register & Bit #Defines File” on page A-29, and a sample of def2192-12.h is shown in “Register and Bit #Defines File” on page B-95. Many registers have reserved bits. When writing to a register, pro- grams may clear (write zero to) the register’s reserved bits only.
  • Page 3 ADSP-2192 DSP Peripheral Registers DSP Peripherals Architecture Figure B-1 shows the DSP’s on-chip peripherals, which include the Host port (PCI or USB), AC’97 port, JTAG test and emulation port, flags, and interrupt controller. 6+$5(' 0(025< 0(025< ,17(5 5837 &21752//(5 0(025< 7, 0 (5)/$*6 $'63;...
  • Page 4 Peripheral Device Register Groups Peripheral Device Register Groups The registers that control FIFO DMA transfers are accessible only from within the DSP. They are defined as part of the Core Register Space. Summary Each of the DSPs integrated within the ADSP-2192 and the interfaces (PCI, USB Sub-ISA, Cardbus) needs to be capable of controlling and monitoring a variety of registers external to the DSP core.
  • Page 5 ADSP-2192 DSP Peripheral Registers Most AC’97 codec registers may be shadowed, and actual reads should be rare. Example In the worst case, DSP core P1 posts two AC’97 codec register writes just after the start of a new Frame. DSP core P0 immediately follows with a read to an AC’97 codec register.
  • Page 6 ADSP-2192 System Control Registers ADSP-2192 System Control Registers The following tables show the System Control Registers in each DSP core. Table B-1. ADSP-2192 System Control Registers Address Register Function Base Register0 Base Register1 Base Register2 Base Register3 Base Register4 Base Register5 Base Register6 Base Register7 08 - 0B...
  • Page 7 ADSP-2192 DSP Peripheral Registers Table B-1. ADSP-2192 System Control Registers (Continued) Address Register Function 14 - 1F Reserved STCTL1 FIFO1 Transmit Control Register SRCTL1 FIFO1 Receive Control Register FIFO1 Transmit Data (TX) register FIFO1 Receive Data (RX) register 24 - 2F Reserved TPERIOD Timer Period Register...
  • Page 8 ADSP-2192 System Control Registers Table B-1. ADSP-2192 System Control Registers (Continued) Address Register Function TX0CNT DMA Count, FIFO0 Transmit TX0CURCNT DMA Current Count, FIFO0 Transmit RX0ADDR DMA Address, FIFO0 Receive RX0NXTADDR DMA Next Address, FIFO0 Receive RX0CNT DMA Count, FIFO0 Receive RX0CURCNT DMA Current Count, FIFO0 Receive TX1ADDR...
  • Page 9 ADSP-2192 DSP Peripheral Registers Table B-1. ADSP-2192 System Control Registers (Continued) Address Register Function CNT2 Cycle Counter 2 Register CNT3 Cycle Counter 3 Register (MSB) 66-FF Reserved STCTLx FIFO Transmit Control Register These include the STCTL0 STCTL1 registers in each DSP core. SRCTLx FIFO Receive Control Register These include the SRCTL0...
  • Page 10 ADSP-2192 System Control Registers xxxADDR DMA Address Register This group of registers include Rx0ADDR Rx1ADDR Tx0ADDR Tx1ADDR , and MAS- TADDR registers for each DSP core. Each register is a 16-bit register containing a 16-bit word. xxxNXTADDR DMA Next Address Register Rx0NXTADDR Rx1NXTADDR Tx0NXTADDR...
  • Page 11 ADSP-2192 DSP Peripheral Registers ADSP-2192 Peripheral Device Control Registers The following tables show the Peripheral Device Control Registers accessi- ble by both DSP cores and the PCI and USB interfaces. The following is a summary of the various classes of I/O registers and their organization within DSP I/O pages.
  • Page 12 ADSP-2192 Peripheral Device Control Registers Table B-2. Register Group Descriptions (Continued) Page Addresses Descriptions Access Refer to permitted by 0x05 0x00-0x7E AC’97 Codec Register DSP / PCI / USB page B-45 Space, Secondary Codec 1 0x06 0x00-0x7E AC’97 Codec Register DSP / PCI / USB page B-46 Space,...
  • Page 13 ADSP-2192 DSP Peripheral Registers ADSP-2192 Chip Control Registers The chip control registers provide support for the following: • General status for the chip as a whole • Power-down operations • Other control functions The following table lists the PDC register space. The register addresses from PCI space, USB space, and DSP I/O space are listed.
  • Page 14 ADSP-2192 Peripheral Device Control Registers Chip Control (SYSCON) Registers Table B-4. SYSCON Register Bit Descriptions Bit Position Bit Name Description Soft Chip Reset. A write of 1 causes a soft reset to the ADSP-2192. A write of 0 has no effect. Always reads 0. Soft Reset affects the DSPs and the GPIOs.
  • Page 15 ADSP-2192 DSP Peripheral Registers Table B-4. SYSCON Register Bit Descriptions (Continued) Bit Position Bit Name Description RDIS Reset Disable. When 1, disables a PCI/ISA/CBUS bus reset from affecting any portions of the ADSP-2192 except the bus interface itself. When 0 (default), a bus reset causes the DSPs and AC’97 subsystem to be reset.
  • Page 16 ADSP-2192 Peripheral Device Control Registers Table B-4. SYSCON Register Bit Descriptions (Continued) Bit Position Bit Name Description ACVX AC’97 External Devices Vaux Powered. Controls the AC’97 interface during D3cold (RST asserted). 0 = Disable the interface (drive 0, disable all inputs). This is used if external AC’97 devices are NOT powered during d3cold, and protects the ADSP-2192 from floating inputs and from outputs driving input clamps...
  • Page 17 ADSP-2192 DSP Peripheral Registers Table B-4. SYSCON Register Bit Descriptions (Continued) Bit Position Bit Name Description 11:10 BUS<1:0> Bus Mode. Mode Pin status. Sampled at Power-On Reset (Read-Only). 00= PCI 01= CardBus 10= USB 11= Sub-ISA AC’97 5V level. If the AC’97 interface is powered from nominal 5V;...

  • Page 18: Power Management Functions

    ADSP-2192 Peripheral Device Control Registers Power Management Functions Power management registers share the same bit specifications. Each regis- ter corresponds to one of the PCI functions: 13:9 All bits in this register reset to zero. Table B-5. Bit Descriptions for PWRCFG0, PWRCFG1, and PWRCFG2 Registers Bit Position Bit Name...
  • Page 19 ADSP-2192 DSP Peripheral Registers Table B-5. Bit Descriptions for PWRCFG0, PWRCFG1, and PWRCFG2 Registers (Continued) Bit Position Bit Name Description SPME Power Management Event (Set). A write of 1 to this bit sets the PME bit for this function. A write of 0 has no effect. Always reads 0.
  • Page 20 ADSP-2192 Peripheral Device Control Registers Table B-6. DSP Interrupt/Powerdown (PWRPx) Register Bit Descriptions Bit Position Bit Name Description DSP PowerDown. When written to a 1, causes the DSP to power down (enter its power-down handler). Can also be used to abort a power-up: if the DSP is in the power-down handler after executing an IDLE, writing a 1 will cause the DSP to immediately re-enter the PowerDown interrupt handler after it executes the RTI.
  • Page 21 ADSP-2192 DSP Peripheral Registers Table B-6. DSP Interrupt/Powerdown (PWRPx) Register Bit Descriptions (Continued) Bit Position Bit Name Description RSTD DSP Soft Reset When written to a 1, causes a soft reset to this DSP. Retains a 1 until cleared by writing to a 0. If the DSP core is powered down, it must be powered up first (DSP:PU bit written to 1) before resetting.
  • Page 22 ADSP-2192 Peripheral Device Control Registers Table B-6. DSP Interrupt/Powerdown (PWRPx) Register Bit Descriptions (Continued) Bit Position Bit Name Description AIEN DSP Interrupt Enable: AC’97 Interrupt. When 1, enables an IO interrupt to this DSP from the AC’97 port. If 0, no interrupt will be signalled and the correspond- ing Interrupt Pending bit will not be set upon an event.
  • Page 23 ADSP-2192 DSP Peripheral Registers DSP PLL Control (PLLCTL) Register The DSP PLL control register controls the frequencies of the PLL (Phase Locked Loop) clock generator. Do not write to this register unless the PLL is powered down. The register is controlled by an Adjust bit. When the Adjust bit is zero, default values for the settings in that segment are used by the PLL.
  • Page 24 ADSP-2192 Peripheral Device Control Registers General Purpose I/O (GPIO) Control Registers Eight pins support general-purpose I/O to registers that control them. Table B-7 lists the Peripheral Device Control Register Space for GPIO Control registers: Table B-7. GPIO Control Registers Register Description Name Address...
  • Page 25 ADSP-2192 DSP Peripheral Registers Table B-7. GPIO Control Registers (Continued) Register Description Name Address Address Page Address GPIOPUP GPIO Pullup 0x01C 0x001C 0x00 0x1C Pull-up enable (if input): 1 = enable, 0 = Hi-Z GPIOPDN GPIO Pulldown 0x01E 0x001E 0x00 0x1E Pull-down enable (if input): 1 = enable, 0 =...
  • Page 26 ADSP-2192 Peripheral Device Control Registers GPIO Sticky (GPIOSTKY) Register This register resets to zero. GPIO Wakeup Control (GPIOWAKECTL) Register This register resets to zero. GPIO Status (GPIOSTAT) Register This register resets to 0xFF. B-26 ADSP-219x/2192 DSP Hardware Reference...
  • Page 27 ADSP-2192 DSP Peripheral Registers GPIO Control (GPIOCTL) Register This register resets to 0x7F. GPIO Pullup (GPIOPUP) Register This register resets to 0xFF. GPIO Pulldown (GPIOPDN) Register This register resets to zero. ADSP-219x/2192 DSP Hardware Reference B-27...
  • Page 28 ADSP-2192 Peripheral Device Control Registers EEPROM I/O Control/Status (SPROMCTL) Register EEPROM register controls access to the serial EEPROM. Table B-8 lists the Peripheral Device Control Register Space for EEPROM Control Register. Table B-8. SPROMCTL Control Register Register Name Description Address Address Page Address...
  • Page 29 ADSP-2192 DSP Peripheral Registers Table B-9. SPROMCTL Register Bit Descriptions Bit Position Bit Name Description Reserved SDA pin status. Default = 0. Note: This bit resets to zero. SEN pin status. Default = 0 (output driving 0). Note: This bit resets to zero. SCK pin status.
  • Page 30 ADSP-2192 Peripheral Device Control Registers Host Mailbox Registers The Host Mailbox registers control communication between the DSP and host (PCI host or USB Host), depending on which one is turned on. Only one can be active at time. Overview DSP Mailbox registers allow you to construct an efficient communications protocol between the PCI device driver and the DSP code.
  • Page 31 ADSP-2192 DSP Peripheral Registers Table B-10 lists the Peripheral Device Control Register Space for PCI/USB Mailbox registers. For register bit names and descriptions for each register, see the topic “Using DSP and PCI Mailbox Registers” in Chapter 6 Dual DSP Cores.
  • Page 32 ADSP-2192 Peripheral Device Control Registers CardBus Function Event Registers Of the four function modes, PCI, USB, sub-ISA, and Cardbus, these function event registers are used only in CardBus mode to provide status registers for power management. BUSMODE=01 In a CardBus system (specified by ), the operating system han- dles Power Management in one of two ways.
  • Page 33 ADSP-2192 DSP Peripheral Registers The CardBus Function Event registers are defined to inter-operate with SYSCON the PCI Power Management Control/Status ( ) register as follows: PME_EN • PCI updates bit. CardBus GWAKM WKUPM take the new value. PME_Status • PCI clears (writes 1).
  • Page 34 ADSP-2192 Peripheral Device Control Registers • The function’s GWAKEM general wakeup bit is 1 • The function’s GWAKEE general-wake event pending bit is 1 GWAKE is an alias of the function’s SYSCON:PME_Status latch. GWAKEE is set to 1 when any of the conditions occurs which would set PME_Status for that function, according to the masks in the function’s Function Power Man-...
  • Page 35 ADSP-2192 DSP Peripheral Registers CIS Tuple Requirements The four Function Event Registers for each function are pointed to by a data structure in CIS (Card Information Services) RAM, which must be initialized by the DSP from ROM at power-up. A CISTPL_CONFIG_CB CIS tuple must be provided for each function to point to the function event registers in BAR1 at the appropriate off-...
  • Page 36 ADSP-2192 Peripheral Device Control Registers CardBus Function Event (CB_FE0) Register All bits in this register are reset to zero. Table B-12. CB_FE0 Register Bit Description Bit Position Bit Name Description Reserved GWKE General Wakeup Event Pending. This bit is equivalent to the PME_Status bit. It reads 1 if CB_FPS0:GWAKE has been set by either a wakeup event on AC’97 as enabled by APME, or by a wakeup event on GPIOs enabled by GPME.
  • Page 37 ADSP-2192 DSP Peripheral Registers CardBus Function Event Mask (CB_FEM0) Register All bits in this register are reset to zero. Table B-13. CB_FEM0 Register Bit Descriptions Bit Position Bit Name Description Reserved GWKM General Wakeup Mask. This bit is equivalent to PME_Enable. Enables assertion of CSTSCHG in Cardbus mode (see above).
  • Page 38 ADSP-2192 Peripheral Device Control Registers Table B-13. CB_FEM0 Register Bit Descriptions (Continued) Bit Position Bit Name Description INTM Interrupt / Wakeup Mask. Enables assertion of INTA and PME//CSTSCHG when in Card- Bus mode (CBUS = low). Has no effect upon INTA or PME/CSTSCHG when not in CardBus mode.
  • Page 39 ADSP-2192 DSP Peripheral Registers Table B-14. CB_FPS0 Register Bit Descriptions (Continued) Bit Position Bit Name Description INTR Current Interrupt State. This bit reflects the combined state of the current inter- rupt inputs to DSPI, WKI, GPI, and TABI. Table B-15. CardBus Function Event Registers Register Name Description Address...
  • Page 40 ADSP-2192 Peripheral Device Control Registers Table B-15. CardBus Function Event Registers Register Name Description Address Address Page Address Function 2 Present 0x12B-0x128 0x01 0x28 CBPRES_STATE2 State Function 2 Event 0x12F-0x12C 0x01 0x2C CBEVENT_FORCE2 Force CardBus Function Event Force (CB_FEFx) Register Table B-16.
  • Page 41 ADSP-2192 DSP Peripheral Registers AC’97 Controller Registers These control registers for the serial port are used for audio (sound) and modem, specifically V.90 modems under codec control. Table B-17. AC’97 Control Registers Register Description USB Address Name Address Page Address AC97LCTL AC’97 Link 0x0C1-0x0C0...
  • Page 42 ADSP-2192 Peripheral Device Control Registers Table B-17. AC’97 Control Registers (Continued) Register Description USB Address Name Address Page Address AC97SIF AC’97 External 0x0CB-0x0CA 0x00CB-0x00CA 0x00 0xCA GPIO Status Register GPIO slot 12 interface register AC’97 Link Control/Status Register (AC97LCTL) AC’97 Link Status Register (AC97STAT) The following illustration shows the AC’97 Link Status Register Bit Definitions All the bits in this register reset to zero.
  • Page 43 ADSP-2192 DSP Peripheral Registers AC’97 Slot Enable Register (AC97SEN) The numbers indicated after the bit name (ACSE12, for example) indicate the relative slot number. Slots are numbered in increasing order (0 first), while bits are numbered in decreasing order (MSB first). The bits in the ACSE register reset to zero.
  • Page 44 ADSP-2192 Peripheral Device Control Registers AC’97 Slot Request Register (AC97SREQ) The numbers indicated after the bit name ( ACRQ12 , for example) indicate the relative slot number. Slots are numbered in increasing order (0 first), and bits are numbered in decreasing order (MSB first). The bits in the AC97SREQ register reset to zero.
  • Page 45 ADSP-2192 DSP Peripheral Registers AC’97 Codec Registers These register spaces are used to access registers in external codecs that are connected to the AC’97 port. Refer to the standard list provided in docu- mentation for your codec. The IDs associated with primary, secondary, and tertiary registers report addressing information available for accessing the codecs.

  • Page 46: Dma Control Registers

    ADSP-2192 Peripheral Device Control Registers AC’97 Codec Register Space, Secondary Codec 2 (AC97EXT2) Register Table B-20. AC’97 External Codec Space 2 Registers Register Description USB Address Name Address Page Address AC97EXT2 AC’97 External 0x67F-0x600 0x067F-0x0600 0x06 0x7F-0x00 Codec Space 2. External Second- ary Codec 2 Reg- ister...
  • Page 47 ADSP-2192 DSP Peripheral Registers • DMA PCI Control/Status ( • DMA PCI Control/Status ( None of the PCI DMA control registers can be reset. PCI Interrupt, Control Registers Use the PCI registers to access the PCI DSP interface. Table B-21. PCI Interrupt Control Registers Register Name Description Address...
  • Page 48 ADSP-2192 Peripheral Device Control Registers Table B-21. PCI Interrupt Control Registers (Continued) Register Name Description Address Address Page Address PCI_IRQSTAT Interrupt Register 0x889-0x888 No Access. 0x08 0x88 Status bits for all PCI interrupt sources. PCI_CFGCTL PCI Control 0x88A No Access. 0x08 0x8A Includes configura-...
  • Page 49 ADSP-2192 DSP Peripheral Registers DMA Control X - Bus Master Control and Status (PCI_DMACx) Register All bits in this register reset to 0. Table B-22. PCI_DMACx Register Bit Descriptions Bit name Description position DMA EN DMA Enable. WR/RD DMA Write / Read. Flush FIFO Flush Master FIFO.
  • Page 50 ADSP-2192 Peripheral Device Control Registers Table B-22. PCI_DMACx Register Bit Descriptions (Continued) Bit name Description position EMPTY DMA FIFO Empty Status (1 = Empty). HALT DMA Channel Halt Status (1 = Halted). LOOP DMA Channel Loop Status (1 = Looping Occurred). 15:11 Reserved PCI Interrupt (PCI_IRQSTAT) Register...
  • Page 51 ADSP-2192 DSP Peripheral Registers All bits in this register reset to 0. Table B-23. PCI_IRQSTAT Register Bit Descriptions Bit name Description position Reserved Rx0 DMA Channel Interrupt. RX0 DMA Receive Channel 0 Bus Master Transactions Sensitivity: Edge Rx1 DMA Channel Interrupt. RX1 DMA Receive Channel 1 Bus Master Transactions Sensitivity: Edge...
  • Page 52 ADSP-2192 Peripheral Device Control Registers Table B-23. PCI_IRQSTAT Register Bit Descriptions (Continued) Bit name Description position MBox 0 IN Incoming Mailbox 0 PCI Interrupt. PCI to DSP Mailbox 0 Transfer Sensitivity: Edge MBox 1 IN Incoming Mailbox 1 PCI Interrupt. PCI to DSP Mailbox 1 Transfer Sensitivity: Edge MBox 0 OUT Outgoing Mailbox 0 PCI Interrupt.
  • Page 53 ADSP-2192 DSP Peripheral Registers PCI Control (PCI_CFGCTL) Register All bits in this register reset to 0. Table B-24. PCI_CFGCTL Register Bit Descriptions Bit name Description position PCIF[1:0] PCI Functions Configured. 00 = One PCI Function enabled 01= Two functions 10= Three functions Conf Rdy Configuration Ready.
  • Page 54 ADSP-2192 Peripheral Device Control Registers Table B-24. PCI_CFGCTL Register Bit Descriptions (Continued) Bit name Description position Reserved Reserved Reserved GPIO IEN General Purpose I/O Pin Initiated Interrupt Enabled. AC’97 IEN AC’97 Interface Initiated Interrupt Enabled. MAbort IEN PCI Interface Master Abort Detect Interrupt Enabled. TAbort IEN PCI Interface Target Abort Detect Interrupt Enabled.
  • Page 55 ADSP-2192 DSP Peripheral Registers Each function contains four base address registers that access ADSP-2192 control registers and DSP memory. Base address register (BAR1) accesses the ADSP-2192 control registers. Accesses to the control registers via BAR1 use PCI memory accesses. BAR1 requests a memory allocation of 1024 bytes.
  • Page 56 ADSP-2192 Peripheral Device Control Registers Within the Power Management section of the configuration blocks, there are a few interactions. The part will stay in the highest power state between the three functions. Thus if a modem is requested to be powered down to state but Function 0 is set for power state , the overall chip...
  • Page 57 ADSP-2192 DSP Peripheral Registers Table B-25. Function 0 Registers (Continued) Register Name Description Address Address Page Address PCI_CFG0_CCODEL Config0 Class 0x08 0x09 0x08 Code[7:0],Rev PCI_CFG0_CCODEH Config0 Class 0x0B-0x0A 0x09 0x0A Code[23:8] PCI_CFG0_SVID Config0 Sub- 0x2D-0x2C 0x09 0x2C system Vendor ID PCI_CFG0_SDID Config0 Sub- 0x2F-0x2E...
  • Page 58 ADSP-2192 Peripheral Device Control Registers PCI Configuration Register Space, Function 1 PCI Configuration Spaces should be accessed only by the DSP, and only during the boot process. After the PCI interface has been configured, bit 2 PCI_CFGCTL ConfRdy of the register ( ) should be set by the DSP.
  • Page 59 ADSP-2192 DSP Peripheral Registers Table B-26. Function 1 Registers (Continued) Register Name Description Address Address Page Address PCI_CFG1_PWRMT Config1 Power 0x45-0x44 0x0A 0x44 Mgt Capabilities Bit 15 set, if Vaux is sensed valid. PCI Configuration Register Space, Function 2 PCI Configuration Spaces should be accessed only by the DSP, and only during the boot process.

  • Page 60: Pci Configuration Space

    ADSP-2192 Peripheral Device Control Registers Table B-27. Function 2 Registers (Continued) Register Name Description DSP I/O Address Address Address Page PCI_CFG2_CCODEH Config2 Class 0x0B-0x0A 0x0B 0x0A Code[23:8] PCI_CFG2_SVID Config2 Sub- 0x2D-0x2C 0x0B 0x2C system Vendor PCI_CFG2_SDID Config2 Sub- 0x2F-0x2E 0x0B 0x2E system Device PCI_CFG2_PWRMT...
  • Page 61 ADSP-2192 DSP Peripheral Registers Table B-28. PCI CONFIG SPACE for Function 0 (Continued) Address Name Reset Comments 0x05-0x04 Command Register Bus Master, Memory Space Capable, I/O Space Capable 0x07-0x06 Status Register Bits enabled: Capabilities List, Fast B2B, Medium Decode 0x08 Revision ID Writable from the DSP during initial- ization...
  • Page 62 ADSP-2192 Peripheral Device Control Registers Table B-28. PCI CONFIG SPACE for Function 0 (Continued) Address Name Reset Comments 0x2D-0x2C Subsystem Vendor ID 0x11D4 Writable from the DSP during initial- ization 0x2F-0x2E Subsystem Device ID 0x2192 Writable from the DSP during initial- ization 0x33-0x30 Expansion ROM Base...
  • Page 63 ADSP-2192 DSP Peripheral Registers Table B-29. PCI Configuration Space for Function 1 Address Name Reset Comments 0x01-0x00 Vendor ID 0x11D4 Writable from the DSP during initial- ization 0x03-0x02 Device ID 0x219A Writable from the DSP during initial- ization 0x05-0x04 Command Register Bus Master, Memory Space Capable, I/O Space Capable 0x07-0x06...
  • Page 64 ADSP-2192 Peripheral Device Control Registers Table B-29. PCI Configuration Space for Function 1 (Continued) Address Name Reset Comments 0x23-0x20 Base Address5 Unimplemented 0x27-0x24 Base Address 6 Unimplemented 0x2B-0x28 Cardbus CIS Pointer 0x1FE03 CIS RAM Pointer - Function 1 (Read Only). 0x2D-0x2C Subsystem Vendor ID 0x11D4...
  • Page 65 ADSP-2192 DSP Peripheral Registers Table B-30. PCI Configuration Space for Function 2 Address Name Reset Comments 0x01-0x00 Vendor ID 0x11D4 Writable from the DSP during initial- ization 0x03-0x02 Device ID 0x219E Writable from the DSP during initial- ization 0x05-0x04 Command Register Bus Master, Memory Space Capable, I/O Space Capable 0x07-0x06...
  • Page 66 ADSP-2192 Peripheral Device Control Registers Table B-30. PCI Configuration Space for Function 2 (Continued) Address Name Reset Comments 0x23-0x20 Base Address 5 Unimplemented 0x27-0x24 Base Address 5 Unimplemented 0x2B-0x28 Cardbus CIS Pointer 0x1FD03 CIS RAM Pointer - Function 2 (Read Only).
  • Page 67 ADSP-2192 DSP Peripheral Registers Interaction Between Registers Table B-31 on page B-67 Table B-32 on page B-70 show the register interactions between functions. Table B-31. Configuration Space Register Interactions Between Functions Name Comments Vendor ID Separate registers, no interaction Device ID Separate registers, no interaction GROUP Description...
  • Page 68 ADSP-2192 Peripheral Device Control Registers Table B-31. Configuration Space Register Interactions Between Functions (Continued) Name Comments If any function enables SERR driver, then SERR# Enable SERR may be asserted Fast Back-to-back No function generates fast back-to-back Enable transactions Status Register Capabilities List Read-only Bits...
  • Page 69 ADSP-2192 DSP Peripheral Registers Table B-31. Configuration Space Register Interactions Between Functions (Continued) Name Comments Revision ID Read-only Class Code Separate registers, no interaction Cache Line Size Read-only Latency Timer Separate for each function, no interac- tion Header Type Read-only Base Address 1 In range signal ORed between func- tions, any function can access memory...
  • Page 70 ADSP-2192 Peripheral Device Control Registers Table B-32. Power Management Register Interactions Between Functions Name Comments Capability ID Read-only Next_Cap_Ptr Read-only Power Version Read-only Management Capabilities Bits PME Clock Read-only Reserved Read-only Device Specific Ini- Read-only tialization Aux Current Read-only by PCI, writable by DSP D1 Support Read-only D2 Support...
  • Page 71 ADSP-2192 DSP Peripheral Registers Table B-32. Power Management Register Interactions Between Functions (Continued) Name Comments Data Scale 14-13 Read-only, no interaction PME Status Separate for each function, may be set in all functions by a wakeup USB DSP Registers Overview The USB registers control the USB interface, specifically the operation and configuration of the USB Interface.
  • Page 72 ADSP-2192 Peripheral Device Control Registers DSP Register Definitions For each endpoint, four registers are defined in order to provide a memory buffer in the DSP. These registers are defined for each endpoint shared by all interfaces that are defined for a total of 4x8 = 32 registers. These regis- ters are read/write by the DSP only.
  • Page 73 ADSP-2192 DSP Peripheral Registers Table B-33. USB DSP Register Definitions (Continued) Page Address Name 0x0C 0x44-0x45 DSP Memory Buffer Size EP8 0x0C 0x46-0x47 DSP Memory Buffer RD Offset EP8 0x0C 0x48-0x49 DSP Memory Buffer WR Offset EP8 0x0C 0x50-0x53 DSP Memory Buffer Base Addr EP9 0x0C 0x54-0x55 DSP Memory Buffer Size EP9...
  • Page 74 ADSP-2192 Peripheral Device Control Registers DSP Memory Buffer Base Addr Register Figure B-2. DSP Memory Buffer Base Addr Register most significant word least significant word Points to the base address for the DSP memory buffer assigned to this Endpoint. Table B-34. DSP Memory Buffer Base Addr Register [DS, BA16:0] Memory Buffer Base Address DSP Memory select bit.
  • Page 75 ADSP-2192 DSP Peripheral Registers DSP Memory Buffer Size Register Figure B-3. DSP Memory Buffer Size Register Indicates the size of the DSP memory buffer assigned to this Endpoint. Table B-35. DSP Memory Buffer Size Register SZ[15:0] Memory Buffer Size DSP Memory Buffer RD Pointer Offset Register Figure B-4.
  • Page 76 ADSP-2192 Peripheral Device Control Registers DSP Memory Buffer WR Pointer Offset Register Figure B-5. DSP Memory Buffer WR Pointer Offset Register The offset from the base address for the write pointer of the memory buffer assigned to this Endpoint. Table B-37. DSP Memory Buffer WR Pointer Offset Register WR[15:0] Memory Buffer WR Offset MCU Register Definitions...
  • Page 77 ADSP-2192 DSP Peripheral Registers Table B-38. USB MCU Register Definitions (Continued) Address Name Comment 0x0010-0x0011 USB SETUP Counter 16 bit counter 0x0012-0x0013 USB Control Misc control including re-attach 0x0014-0x0015 USB Address/Endpoint Address of device/active Endpoint 0x0016-0x0017 USB Frame Number Current frame number 0x1000-0x1001 USB EP4 Description Configures Endpoint...
  • Page 78 ADSP-2192 Peripheral Device Control Registers Table B-38. USB MCU Register Definitions (Continued) Address Name Comment 0x101C-0x101D USB EP11 Description Configures Endpoint 0x101E-0x101F USB EP11 NAK Counter 0x1020-0x1021 USB EP STALL Policy 0x1040-0x1043 USB EP1 Code Download Starting address for code download on End- Base Address point 1 0x1044-0x1047...
  • Page 79 ADSP-2192 DSP Peripheral Registers USB Endpoint Description Register Figure B-6. USB Endpoint Description Register Provides the USB core with information about the Endpoint type, direc- tion, and maximum packet size. This register is read/write by the MCU only. This register is defined for Endpoints[4:11]. Table B-39.
  • Page 80 ADSP-2192 Peripheral Device Control Registers USB Endpoint NAK Counter Register Figure B-7. USB Endpoint NAK Counter Register Contains the individual count, stall control, and counter enable bits for Endpoints 4-11. This register is read/write by the MCU only. Table B-40. USB Endpoint NAK Counter Register NC[3:0] NAK counter.
  • Page 81 ADSP-2192 DSP Peripheral Registers USB Endpoint Stall Policy Register Figure B-8. USB Endpoint Stall Policy Register Contains the base count and FIFO error policy bits for Endpoints 4-11. The STALL status and Data toggle bits for Endpoints 1-3 are included as well.
  • Page 82 ADSP-2192 Peripheral Device Control Registers USB Endpoint 1 Code Download Base Address Register Figure B-9. USB Endpoint 1 Code Download Base Address Register Contains an 18 bit address which corresponds to the starting location for DSP code download on Endpoint 1. This register is read/write by the MCU only.
  • Page 83 ADSP-2192 DSP Peripheral Registers USB Endpoint 2 Code Download Base Address Register Figure B-10. USB Endpoint 2 Code Download Base Address Register Contains an 18 bit address which corresponds to the starting location for DSP code download on Endpoint 2. This register is read/write by the MCU only.
  • Page 84 ADSP-2192 Peripheral Device Control Registers USB Endpoint 3 Code Download Base Address Register Figure B-11. USB Endpoint 3 Code Download Base Address Register Contains an 18 bit address which corresponds to the starting location for DSP code download on Endpoint 3. This register is read/write by the MCU only.
  • Page 85 ADSP-2192 DSP Peripheral Registers USB Endpoint 1 Code Download Current Write Pointer Offset Register Figure B-12. USB Endpoint 1 Code Download Current Write Pointer Offset Register Contains an 18 bit address which corresponds to the current write pointer offset from the base address register for DSP code download on Endpoint 1.
  • Page 86 ADSP-2192 Peripheral Device Control Registers USB Endpoint 2 Code Download Current Write Pointer Offset Register Figure B-13. USB Endpoint 2 Code Download Current Write Pointer Offset Register Contains an 18 bit address which corresponds to the current write pointer offset from the base address register for DSP code download on Endpoint 2.
  • Page 87 ADSP-2192 DSP Peripheral Registers USB Endpoint 3 Code Download Current Write Pointer Offset Register Figure B-14. USB Endpoint 3 Code Download Current Write Pointer Offset Register Contains an 18 bit address which corresponds to the current write pointer offset from the base address register for DSP code download on Endpoint 3.
  • Page 88 ADSP-2192 Peripheral Device Control Registers USB SETUP Token Command Register This register is defined as eight bytes long and contains the data sent on SETUP the USB from the most recent transaction. This register is read by the MCU only. Table B-42.
  • Page 89 ADSP-2192 DSP Peripheral Registers USB SETUP Token Data Register If the most recent SETUP transaction involves a data OUT stage, the USB SETUP Token Data Register is defined as eight bytes long and contains the data sent on the USB during the data stage. This is also where the MCU will write data to be sent in response to a SETUP transaction involving...
  • Page 90 ADSP-2192 Peripheral Device Control Registers USB SETUP Counter Register Figure B-15. USB SETUP Counter Register Provides information as to the total size of the SETUP transaction data stage. This register is read/write by the MCU only. C[3:0] Counter bits. The counter hardware is a modulo 4 bit down counter used for tallying data bytes in both the IN and OUT data stages of SETUP transactions.
  • Page 91 ADSP-2192 DSP Peripheral Registers USB Register I/O Address Register Figure B-16. USB Register I/O Address Register Contains the address of the ADSP-2192 register that is to be read/written. This register is read/write by the MCU only. Table B-44. USB Register I/O Address Register A[15] MCU sets to 1 to notify the PDC Register Interface block to start ADSP-2192 read/write cycle.

  • Page 92: Usb Control Register

    ADSP-2192 Peripheral Device Control Registers USB Register I/O Data Register Figure B-17. USB Register I/O Data Register Contains the data of the ADSP-2192 register which has been read or is to be written. This register is read/write by the MCU only. Table B-45.
  • Page 93 ADSP-2192 DSP Peripheral Registers Table B-46. USB Control Register A value of 1 means: After reset boot from MCU RAM, 0 = after reset boot from MCU ROM A value of 1 means: Enables remote wake-up capability, 0 = disables remote wake-up capability Active interrupt for the 8051 MCU Current interrupt is for a SETUP token...

  • Page 94: Usb Frame Number Register

    ADSP-2192 Peripheral Device Control Registers USB Address/Endpoint Register Figure B-19. USB Address/Endpoint Register Contains the USB address and active Endpoint. This register is read/write by the MCU only. Table B-47. USB Address/Endpoint Register A[6:0] USB address assigned to device EP[3:0] USB last active Endpoint USB Frame Number Register Figure B-20.
  • Page 95 The version of the file that appears here is included as a guide only. ----------------------------------------------------------------------- def2192-12.h - SYSTEM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-2192-12 Copyright (c) 2001 Analog Devices, Inc., All rights reserved The def2192-12.h file defines ALL ADSP-2192-12 DSP symbolic names. -----------------------------------------------------------------------...
  • Page 96 Register and Bit #Defines File #define INT_INT14_P 14 // Bit 14: Offset: 38: Unused #define INT_AC97FR_P 15 // Bit 15: Offset: 3c: AC97 serial port // Bit Masks #define INT_MAILBXI MK_BMSK_(INT_MAILBXI_P) // Offset: 10: Mailbox #define INT_TMZHI MK_BMSK_(INT_TMZHI_P) // Offset: 14: Timer // (High Priority) #define INT_INT6 MK_BMSK_(INT_INT6_P) // Offset: 18: Unused #define INT_PCIBMI MK_BMSK_(INT_PCIBMI_P) // Offset: 1c: PCI...
  • Page 97 ADSP-2192 DSP Peripheral Registers #define SCTL_SSEL2 MK_BMSK_(SCTL_SSEL2_P) // AC'97 Slot Select #define SCTL_SSEL1 MK_BMSK_(SCTL_SSEL1_P) // AC'97 Slot Select #define SCTL_SSEL0 MK_BMSK_(SCTL_SSEL0_P) // AC'97 Slot Select #define SCTL_FIP2 MK_BMSK_(SCTL_FIP2_P ) // AC'97 FIFO Interrupt Position #define SCTL_FIP1 MK_BMSK_(SCTL_FIP1_P ) // AC'97 FIFO Interrupt Position #define SCTL_FIP0 MK_BMSK_(SCTL_FIP0_P ) // AC'97 FIFO Interrupt Position #define SCTL_SDEN MK_BMSK_(SCTL_SDEN_P ) // AC'97 Port DMA Enable...
  • Page 98 Register and Bit #Defines File #define SCON_RDIS_P 2 // Reset Disable #define SCON_RST_P 0 // Soft Chip Reset // Bit Masks #define SCON_PCIRST MK_BMSK_(SCON_PCIRST_P) // PCI Reset #define SCON_VAUX MK_BMSK_(SCON_VAUX_P ) // Vaux Present #define SCON_PCI_5V MK_BMSK_(SCON_PCI_5V_P) // PCI 5V level #define SCON_BUS1 MK_BMSK_(SCON_BUS1_P ) // Bus Mode #define SCON_BUS0...
  • Page 99 ADSP-2192 DSP Peripheral Registers #define PWRP_GWE MK_BMSK_(PWRP_GWE_P // DSP Wake up on GPIO // Input Enable #define PWRP_PMWE MK_BMSK_(PWRP_PMWE_P ) // Power Management // Wake up Enable #define PWRP_RSTD MK_BMSK_(PWRP_RSTD_P ) // DSP Soft Reset #define PWRP_PU MK_BMSK_(PWRP_PU_P // DSP Power Up #define PWRP_PD MK_BMSK_(PWRP_PD_P // DSP Power Down...
  • Page 100 Register and Bit #Defines File // Bit Masks #define PWRC_SPME MK_BMSK_(PWRC_SPME_P) // DSP PLL N Divisor Selects #define PWRC_GPME MK_BMSK_(PWRC_GPME_P) // DSP PLL N Divisor Selects #define PWRC_PWRST1 MK_BMSK_(PWRC_PWRST1_P) // DSP PLL K Divisor Selects #define PWRC_PWRST0 MK_BMSK_(PWRC_PWRST0_P) // DSP PLL K Divisor Selects //---------------------------------------------------------------------- System Register address definitions //----------------------------------------------------------------------...
  • Page 101 ADSP-2192 DSP Peripheral Registers #define TX1ADDR 0x50 // DMA Address, Fifo1 Transmit #define TX1NXTADDR 0x51 // DMA Next Address, Fifo1 Transmit #define TX1CNT 0x52 // DMA Count, Fifo1 Transmit #define TX1CURCNT 0x53 // DMA Current Count, Fifo1 Transmit #define RX1ADDR 0x54 // DMA Address, Fifo1 Receive...
  • Page 102 Register and Bit #Defines File AC'97 Control Registers (DSP IOPAGE=0x00) #define AC97LCTL 0xC0 AC'97 Link Control #define AC97LSTAT 0xC2 AC'97 Link Status #define AC97SEN 0xC4 AC'97 Slot Enable #define AC97SVAL 0xC6 AC'97 Input Slot Valid #define AC97SREQ 0xC8 AC'97 Slot Request #define AC97GPIO 0xCA AC'97 External GPIO Register...
  • Page 103 ADSP-2192 DSP Peripheral Registers #define PCI_Rx0CURCNTH 0x0E // Rx0 DMA Current Count Bits 31:16 #define PCI_Tx0BADDRL 0x10 Tx0 DMA Base Address Bits 15:0 #define PCI_Tx0BADDRH 0x12 // Tx0 DMA Base Address Bits 31:16 #define PCI_Tx0CURADDRL 0x14 Tx0 DMA Current Address Bits 15:0 #define PCI_Tx0CURADDRH 0x16 // Tx0 DMA Current Address...
  • Page 104 Register and Bit #Defines File #define PCI_Tx1IRQCNTL 0x58 // Tx1 DMA Interrupt Count Bits 15:0 #define PCI_Tx1IRQCNTH 0x5A // Tx1 DMA Interrupt Count Bits 23:16 #define PCI_Tx1IRQBCNTL 0x5C Tx1 DMA Interrupt Base Count Bits 15:0 #define PCI_Tx1IRQBCNTH 0x5E // Tx1 DMA Interrupt Base Count Bits 23:16 #define PCI_Rx0CTL 0x60 Rx0 DMA PCI Control/Status...
  • Page 105 ADSP-2192 DSP Peripheral Registers #define PCI_ClassCODE1L 0x08 // Configuration 1 Class Code[7:0], Rev ID #define PCI_ClassCODE1H 0x0A // Configuration 1 Class Code[23:8] #define PCI_SvendorID1 0x2C // Configuration 1 Subsystem Vendor ID #define PCI_SdeviceID1 0x2E // Configuration 1 Subsystem Device ID #define PCI_PWRMT1 0x44 // Configuration 1...
  • Page 106 Register and Bit #Defines File #define USB_EP8_SIZE 0x44 // Memory Buffer Size EP8 #define USB_EP8_RD 0x46 // Memory Buffer RD Offset EP8 #define USB_EP8_WR 0x48 // Memory Buffer WR Offset EP8 #define USB_EP9_ADDR 0x50 // Memory Buffer Base Addr. EP9 #define USB_EP9_SIZE 0x54 // Memory Buffer Size EP9...

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