Dma Throughput - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DMA Throughput

Table 7-15. Link to Link TCB
Receiver TCB Configuration
Register Field
DI
DX
DY
DP TY
DP PR
DP 2DDMA
DP LEN
DP INT
DP DRQ
DP CHEN
DP CHTG
DP CHPT
DMA Throughput
This section discusses overall DMA throughput when several DMA chan-
nels are trying to access internal or external memory at the same time.
7-66
Description
Link port address
• 0x1804A0 for link #0
• 0x1804A8 for link #1
• 0x1804B0 for link #2
• 0x1804B8 for link #3
Number of words to transfer and address modifier – the address modifier
must be set to 0.
Irrelevant
I/O link ports or DMA data registers
Channel priority
1 – Increases the channel priority—internal bus DMA request
priority is high.
Cleared.
Always set to quad-word.
Sets interrupt
1 – Interrupts the core once the complete block is transferred.
Don't care (set in hardware).
Sets chaining
1 – Enables chaining.
Defines register to be loaded; may be any link channel.
TCB
Chaining pointer – relevant if chaining is enabled.
ADSP-TS101 TigerSHARC Processor
Hardware Reference