Dag Stalls; Memory Stalls; Iop Register Stalls; Dma Stalls - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Core Stalls
• Any read reference to a memory-mapped register located within a
peripheral such as the SPI, SPORTS, IDP, or parallel port requires
a minimum of four cycles; so the minimum stall is three cycles.
• Any reference to a memory-mapped register in a conditional
instruction stalls the processor for one extra cycle (with respect to
an unconditional instruction).

DAG Stalls

One cycle hold on register conflict.

Memory Stalls

One cycle on PM and DM bus access to the same block of internal
memory.

IOP Register Stalls

Read of the IOP registers takes a minimum of four cycles, therefore the
processor stalls for at least three cycles.

DMA Stalls

The following events can cause a DMA stall for the ADSP-2126x:
• One cycle stall if an access to a DMA Parameter register conflicts
with the DMA address generation. For example, writing to or read-
ing from a DMA Parameter register while a register update is
taking place conflicts with DMA chaining.
• n cycles if writing (or reading) to a DMA buffer when the buffer is
full (or empty).
3-24 ADSP-2126x SHARC Processor Hardware Reference