Reverse Parallel Loopback; Serial Loopback - Altera Cyclone IV Device Handbook

Chapter 1: Cyclone IV Transceivers Architecture
Loopback

Reverse Parallel Loopback

The reverse parallel loopback option is only available for PIPE mode. In this mode,
the received serial data passes through the receiver CDR, deserializer, word aligner,
and rate match FIFO before looping back to the transmitter serializer and transmitted
out through the TX buffer, as shown in
to the FPGA fabric. This loopback mode is compliant with version 2.00 of the
Interface for the PCI Express Architecture
To enable the reverse parallel loopback mode, assert the tx_detectrxloopback port in
P0 power state.
Figure 1–70. PIPE Reverse Parallel Loopback Path
Transceiver
FPGA
Fabric
PCIe
hard
IP
Note to Figure 1–70:
(1) Grayed-Out Blocks are Not Active in this mode.

Serial Loopback

The serial loopback option is available for all functional modes except PIPE mode. In
this mode, the data from the FPGA fabric passes through the transmitter channel and
looped back to the receiver channel, bypassing the receiver buffer, as shown in
Figure
receiver input buffer is not active in this mode. With this option, you can check the
operation of all enabled PCS and PMA functional blocks in the transmitter and
receiver channels.
The transmitter channel sends the data to both the serial output port and the receiver
channel. The differential output voltage on the serial ports is based on the selected
V
OD
different clock domains. You must provide an alignment pattern for the word aligner
to enable the receiver channel to retrieve the byte boundary.
February 2015 Altera Corporation
(1)
PIPE
IF
Rx PCS
1–71. The received data is available to the FPGA logic for verification. The
settings. The data is looped back to the receiver CDR and is retimed through
Figure 1–70. The received data is also available
specification.
Tx PMA
Tx PCS
Serializer
Reverse parallel
loopback path
Rate
Word
Match
Aligner
FIFO
1–79
PHY
Rx PMA
Deserial-
CDR
izer
Cyclone IV Device Handbook,
Volume 2