Transfer Control Block Chain Loading (Tcb) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

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Transfer Control Block Chain Loading (TCB)

During TCB chain loading, the I/O processor loads the DMA channel

parameter registers with values retrieved from internal memory. The

address in the chain pointer register points to the highest address of the

TCB (containing the index parameter). This means that if a program

declares an array to hold the TCB, the

first location of the array. Instead the

shows the TCB-to-register loading sequence for the serial port

and SPI port DMA channels. The I/O processor reads each word of the

TCB and loads it into the corresponding register. Programs must set up

the TCB in memory in the order shown in

parameter at the address pointed to by the

DMA operation of the chain. The end of the chain (no further TCBs are

loaded) is indicated by a TCB with a

Table 7-2. TCB Chain Loading Sequence

CPSPx + 0x0008 0000

CPSPx – 1 + 0x0008 0000

CPSPx – 2 + 0x0008 0000

CPSPx – 3 + 0x0008 0000

1 Chaining is not available using the IDP or parallel ports.

2 An "x" denotes the DMA channel used. While the TCB is eight locations

in length, SPI and serial ports only use the first four locations.

A TCB chain load request is prioritized like all other DMA operations.

The I/O processor latches a TCB loading request and holds it until the

load request has the highest priority. If multiple chaining requests are

present, the I/O processor services the

DMA channel first. A channel that is in the process of chain loading

ADSP-2126x SHARC Processor Hardware Reference

value of zero.

Serial Ports

registers for the highest priority

I/O Processor

7-2, placing the index

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