Eprom Tcb - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DMA Operation on Boot

EPROM TCB

Upon reset, the DMA initiates a transfer by requesting external data from
OFIFO:
• The TigerSHARC processor reads the data from boot EPROM
into its IFIFO.
• The IFIFO gets the return address from the receiver
and initiates an internal write access.
• After transferring the complete block, the DMA interrupts the core
and jumps it to address 0x00000000.
Table 10-5. EPROM Boot – EPROM TCB
Transmitter TCB Configuration
Register Field
DI
DX
DY
DP TY
DP PR
DP 2DDMA
DP LEN
DP INT
DP DRQ
DP CHEN
DP CHTG
DP CHPT
10-34
Description
0x00000000
Number of words to transfer is 256.
Address modifier is set to 0x0004.
0x00000000
Boot EPROM
1
0
Word
1
0
0
0x0
0x00000
ADSP-TS101 TigerSHARC Processor
register
TCB
Hardware Reference