REGISTER 15—TEST MODE REGISTER
ANALOG_TEST_
COx
CAL_OVERRIDE
0
AUTO CAL
1
OVERRIDE GAIN
2
OVERRIDE BW
3
OVERRIDE BW AND GAIN
RD1
REG1_PD
0
NORMAL
1
POWER-DOWN
FH1
0
1
AMx
ANALOG_TEST_MODES
0
BAND GAP VOLTAGE
1
40µA CURRENT FROM REG4
2
FILTER I CHANNEL: STAGE 1
3
FILTER I CHANNEL: STAGE 2
4
FILTER I CHANNEL: STAGE 1
5
FILTER Q CHANNEL: STAGE 1
6
FILTER Q CHANNEL: STAGE 2
7
FILTER Q CHANNEL: STAGE 1
8
ADC REFERENCE VOLTAGE
9
BIAS CURRENT FROM RSSI 5µA
10
FILTER COARSE CAL OSCILLATOR OUTPUT
11
ANALOG RSSI I CHANNE
L
12
OFFSET LOOP +VE FBACK V (I CH)
13
SUMMED OUTPUT OF RSSI RECTIFIER+
14
SUMMED OUTPUT OF RSSI RECTIFIER–
15
BIAS CURRENT FROM BB FILTER
PMx
PLL_TEST_MODES
0
NORMAL OPERATION
1
R DIV
2
N DIV
3
RCNTR/2 ON MUXOUT
4
NCNTR/2 ON MUXOUT
5
ACNTR TO MUXOUT
6
PFD PUMP UP TO MUXOUT
7
PFD PUMP DNTO MUXOUT
8
S DATA TO MUXOUT (OR SREAD)
9
ANALOG LOCK DETECT ON MUXOUT
10
END OF COARSE CAL ON MUXOUT
11
END OF FINE CAL ON MUXOUT
12
FORCE NEW PRESCALER CONFIG
FOR ALL N
13
TEST MUX SELECTS DATA
14
LOCK DETECT PRECISION
15
RESERVED
•
Analog RSSI can be viewed on the TEST_A pin by setting
ANALOG_TEST_MODES (Bits[DB27:DB24]) to 11.
•
Tx_TEST_MODES can be used to enable modulation test.
PLL_TEST_
MODES
MODES
FORCE_LD_HIGH
NORMAL
FORCE
CMx
CLK_MUX ON CLKOUT PIN
0
NORMAL, NO OUTPUT
1
DEMOD CLK
2
CDR CLK
3
SEQ CLK
4
BB OFFSET CLK
Σ-Δ CLK
5
6
ADC CLK
7
TxRxCLK
Figure 77. Register 15—Test Mode Register Map
Σ-Δ_TEST_
PFD/CP_
CLK_MUX
MODES
TEST_MODES
PCx
PFD/CP_TEST_MODES
0
DEFAULT, NO BLEED
1
(+VE) CONSTANT BLEED
2
(–VE) CONSTANT BLEED
3
(–VE) PULSED BLEED
4
(–VE) PULSE BLD, DELAY UP
5
CP PUMP UP
6
CP TRISTATE
7
CP PUMP DN
Σ-Δ_TEST_MODES
SDx
DEFAULT, 3RD-ORDER Σ-Δ, NO DITHER
0
1ST-ORDER Σ-Δ
1
2ND-ORDER Σ-Δ
2
3
DITHER TO FIRST STAGE
4
DITHER TO SECOND STAGE
5
DITHERTO THIRD STAGE
6
DITHER × 8
7
DITHER × 32
TMx
Tx_TEST_MODES
0
NORMAL OPERATION
1
Tx CARRIER ONLY
f
2
Tx +
DEV
f
3
Tx –
DEV
4
Tx "1010" PATTERN
5
Tx PN9 DATA SEQUENCE
6
Tx SWD PATTERN REPEATEDLY
•
The CDR block can be bypassed by setting Rx_TEST_
MODES to 4, 5, or 6, depending on the demodulator used.
Rev. 0 | Page 59 of 60
Tx_TEST_
Rx_TEST_
MODES
MODES
TONE ONLY
TONE ONLY
RTx
Rx_TEST_MODES
0
NORMAL
1
SCLK, SDATA
I,Q
2
REVERSE I,Q
3
I,Q TO TxRxCLK, TxRxDATA
3FSK SLICER ON TxRxDATA
4
CORRELATOR SLICER ON TxRxDATA
5
6
LINEAR SLICER ON TxRxDATA
7
SDATA TO CDR
8
ADDITIONAL FILTERING ON I,Q
9
ENABLE REG 14 DEMOD PARAMETERS
10
POWER DOWN DDT AND ED IN T/4 MODE
11
ENVELOPE DETECTOR WATCHDOG DISABLED
12
RESERVED
13
PROHIBIT CAL ACTIVE
14
FORCE CAL ACTIVE
15
ENABLE DEMOD DURING CAL
ADF7021-V
ADDRESS
BITS
Need help?
Do you have a question about the ADF7021-V and is the answer not in the manual?