Enabling Sport Dma (Sden); Interrupt-Driven Data Transfer Mode; Dma-Driven Data Transfer Mode - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Enabling SPORT DMA (SDEN)

DMA can be enabled or disabled independently on any of the SPORT's
transmit and receive channels.
Between SPORTS and Internal Memory" on page 9-65.
(=1) to enable DMA and set the channel in DMA-driven data
SDEN_B
transfer mode. Clear
channel in an interrupt-driven data transfer mode.

Interrupt-Driven Data Transfer Mode

Both the A and B channels share a common interrupt vector, regardless of
whether they are configured as transmitters or receivers.
The SPORT generates an interrupt in every core clock cycle when the
transmit buffer has a vacancy or the receive buffer has data. To determine
the source of an interrupt, applications must check the transmit or receive
data buffer status bits. For details, see
page 9-73.

DMA-Driven Data Transfer Mode

Each transmitter and receiver has its own DMA registers. For details, see
"Selecting Transmit and Receive Channel Order (FRFS)" on page 9-16
and "Moving Data Between SPORTS and Internal Memory" on
page 9-65. The same DMA channel drives both samples in the pair for the
transmitter or receiver. The software application must stop multiplexing
the left and right channel data received by the receive buffer, because the
left and right data is interleaved in the DMA buffers.
Channel A and B on each SPORT share a common interrupt vector. The
DMA controller generates an interrupt at the end of DMA transfer only.
Figure 9-3 shows the relationship between frame sync (word select), serial
clock, and Left-justified mode data. Timing for word select is the same as
for frame sync.
ADSP-2126x SHARC Processor Hardware Reference
For more information, see "Moving Data
or (=0) to disable DMA and set the
SDEN_A SDEN_B
"Single Word Transfers" on
Serial Ports
Set or
SDEN_A
9-17