Table 2-2. PPI Connections (Cont'd)
Processor PPI Pin
PPI0 SYNC2
PPI0 clock
PPI1 SYNC1
PPI1 SYNC2
PPI1 clock
Video Output (PPI1)
The
interface is configured as output and connects to the on-board
PPI1
video encoder device, ADV7179. The ADV7179 encoder generates three
analog video channels on
nect to
of the encoder's pixel inputs. The encoder's input clock is
P7
0
–
fixed and comes from an on-board 27 MHz oscillator.
The encoder's synchronization signals,
ured as inputs or outputs. Video blanking control signal is at level
and
HSYNC
VSYNC
interface via the
PPI1
Switch (SW2)" on page
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
www.BDTIC.com/ADI
ADSP-BF561 EZ-KIT Lite Hardware Reference
Other Processor
EZ-KIT Lite Function
Function
Timer 9
ADV7179
Configuration Switch (SW2)" on page
A choice of ADV7183A output clock, a local
27 MHz oscillator, or an external clock from
ADSP-BF533/BF561 EZ-KIT Extender
Timer 10
ADV7183A
"Video Configuration Switch (SW2)" on page
Timer 11
ADV7183A
"Video Configuration Switch (SW2)" on page
A choice of ADV7183A output clock, a local
27 MHz oscillator, or an external clock from
ADSP-BF53x/BF561 Blackfin EZ-Extender.
,
DAC A
DAC B
signals can connect to
switch, as described in
SW2
2-10.
. For more information, see
VSYNC
. For more information, see
HSYNC
. For more information, see
VSYNC
, and
. The
DAC C
PPI1
and
, can be config-
HSYNC
VSYNC
and
of the processor's
SYNC1
SYNC2
"Video Configuration
"Video
2-10.
®
board.
2-10.
2-10.
bits
con-
7
0
–
. The
1
2-7
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