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TCB Chain Loading Priority
A TCB chain load request is prioritized like all DMA channels. Therefore,
the TCB chain loading request has the same priority level as the DMA
channel itself. The I/O processor latches a TCB loading request and holds
it until the load request has the highest priority. If multiple chaining
requests are present, the I/O processor services the TCB block for the
highest priority DMA channel first.
A channel that is in the process of chain loading cannot be inter-
rupted by any other request (TCB, DMA channel). The chain
loading sequence is atomic and the I/O bus is locked until all the
DMA parameter registers are loaded. For a list of DMA channels in
priority order, see
Chain Insert Mode (SPORTs Only)
It is possible to insert a single SPORT DMA operation or another DMA
chain within an active SPORT DMA chain. Programs may need to per-
form insertion when a high priority DMA requires service and cannot wait
for the current chain to finish. This is supported only for SPORT DMA
channels only.
For more information, see "Serial Ports" in Chapter 6,
Serial Ports.
DMA Start and Stop Conditions
The difference between single DMA and chained DMA is based on the
auto-linkage process where the DMA's attributes are stored in internal
memory and automatically loaded by the IOP if requested.
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Table
2-9.
I/O Processor
2-25
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