Dma Chaining - Analog Devices ADSP-2106x SHARC User Manual

6 DMA
channels.
The channel immediately after the selected channel will now have the
highest fixed priority, for example (ADSP-21060 & ADSP-21062):
Priority at Reset:
Follow steps 1-4 above to make DMA7 the lowest priority.
New Priority Ordering:
6.3.4

DMA Chaining

DMA chaining allows the ADSP-2106x's DMA controller to
autoinitialize itself between multiple DMA transfers. Using chaining,
you can set up multiple DMA operations in which each operation can
have different attributes.
In chained DMA operations, the ADSP-2106x automatically sets up
another DMA transfer when the entire contents of the current buffer
have been transmitted or received. The chain pointer register (CP) is
used to point to the next set of DMA parameters stored in internal
memory. This new set of parameters is called a transfer control block
(TCB). The ADSP-2106x's DMA controller automatically reads the TCB
from internal memory and loads the values into the channel parameter
registers to set up the next DMA sequence; this process is called TCB
chain loading.
A DMA sequence is defined as the sum of the DMA transfers for a
single channel, from the parameter registers initialization to when the
count register decrements to zero.
Each DMA channel has a chaining enable bit (CHEN) in the
corresponding control register. This bit must be set to 1 to enable
chaining. Writing all zeros to the address field of the chain pointer
register (CP) also disables chaining.
When chaining is enabled, DMA transfers are initiated by writing a
memory address to the CP register. This is also an easy way to start a
single DMA sequence, with no subsequent chained DMAs. The CP
register can be loaded at any time during the DMA sequence—this
allows a DMA channel to have chaining disabled (CP register address
field = 0x0000) until some event occurs that loads the CP register with
a non-zero value. DMA chaining operations may only occur within the
same channel; cross-channel chaining is not supported.
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