Dma Chaining - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DMA Chaining

DMA chaining allows the TigerSHARC processor's DMA controller to
auto-initialize itself between multiple DMA transfers. Using chaining,
multiple DMA operations can be set up, in which each operation can have
different attributes and I/Os.
There are some restrictions on chaining DMA across DMA channels. For
internal/external memory DMA transfers, cross channel DMA is not per-
mitted. DMA processes between internal/external memory can only be
chained within the same channel. Link port DMA processes, however,
may be chained across channels.
!
If chaining across link port DMA channels, the system should
enable the DMA error interrupt. This interrupt should be enabled
to detect cross-channel chaining to an already active channel.
In chained DMA operations, the TigerSHARC processor automatically
sets up another DMA transfer when the entire contents of the current
buffer have been transmitted or received:
• Transfer Control Block (TCB)
The chain pointer (field
point to the next set of DMA parameters stored in internal mem-
ory. The chain target field (
to be initiated.
• TCB chain loading
The DMA controller automatically reads the
memory and loads the values into the channel
up the next DMA sequence at the end of the present one. This pro-
cess is called
ADSP-TS101 TigerSHARC Processor
Hardware Reference
in
CHPT
CHTG
chain loading.
TCB
Direct Memory Access
control register
TCB
) in the indicates the channel
TCB
from internal
TCB
TCB
) is used to
DP
registers to set
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