Standard Dsp Serial Mode - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

The operating mode (
mode/left-justified sample pair mode, and non-I
port/multichannel mode). In multichannel mode, the
register enables the A channels and the
CTLx
register enables the B channels. The data direction bit (
SPMCTLx
selects whether the port is a transmitter or receiver in all the SPORT oper-
ation modes.
If the bit is set (= 1), the SPORT becomes a transmitter and all the
SPTRAN
other control bits are defined accordingly. Similarly, when
SPORT becomes a receiver.
Companding logic is only supported for multi-channel mode and
packed I
2, 4 and 6 A channels. Expansion logic is now available only in
SPORT1, 3, 5 and 7 A channels.
The register is unique in that the name and functionality of its bits
SPCTLx
changes depending on the operation mode selected. In each section that
follows, the bit names associated with the operating modes are described.
Table 5-1 provides values for each of the bits in the SPORT control
( ) registers that must be set in order to configure each specific
SPCTLx
SPORT operation mode. An X in a field indicates that the bit is not sup-
ported for the specified operating mode.
Table 5-1. SPORT Operation Modes
Operating Modes

Standard DSP Serial Mode

2
I S (Tx/Rx on Left Channel
First)
2
I S (Tx/Rx on Right Channel
First)
ADSP-21368 SHARC Processor Hardware Reference
) bit of the
OPMODE
2
S mode. Companding logic is available only for SPORT0,
Bits
OPMODE
0
1
1
register selects between I
SPCTLx
2
S mode (DSP serial
bit in the
MCEB
LAFS FRFS MCEA
0, 1 X 0
0 1 0
0 0 0
Serial Ports
2
S
bit in the
MCEA SPM-
)
SPTRAN
= 0, the
SPTRAN
MCEB SLENx
1
0 3-32
0 8-32
0 8-32
5-11