Slave Direct Reads & Writes - Analog Devices ADSP-2106x SHARC User Manual

Although the bus synchronization scheme allows individual
processors to be reset, the ADSP-2106x with ID=001 may fail to drive
the memory control signals if it is in reset while any other processors
BR
are asserting their x line.
If the ADSP-2106x with ID=001 has asserted
will be synchronized when
to start using the bus while the ADSP-2106xs are still in reset.
If a host processor attempts to reset the ADSP-2106x bus master (which
HBG
is driving the output), the host will immediately lose control of
the bus.
During reset, the ACK line is pulled high internally by the ADSP-2106x
bus master (with a 2 kΩ equivalent resistor).
7.4 SLAVE DIRECT READS & WRITES
The ADSP-2106x bus master can directly access the internal memory
and IOP registers of a slave ADSP-2106x by simply reading or writing
to the appropriate address in multiprocessor memory space—this is
called a direct read or direct write. Each ADSP-2106x bus slave monitors
addresses driven on the external bus and responds to any that fall
within its region of multiprocessor memory space.
These accesses are invisible to the slave ADSP-2106x's core processor
because they are performed through the external port and via the
on-chip I/O bus—not the DM bus or PM bus. (See Figure 8.1 in the
Host Interface chapter.)
This is an important distinction, because it allows the slave's core
processor to continue program execution uninterrupted.
The ADSP-2106x bus master can directly read and write the slave's
IOP registers to send a vector interrupt, for example, or to set up a
DMA transfer.
To read or write 48-bit instruction words, the IWT (Instruction Word
Transfer) bit of the SYSCON register must be set to 1. To read or write
32-bit data words, the IWT bit must be cleared to 0. When this bit is set,
it overrides the IMDWx (Internal Memory Data Width) bit of each
memory block.
www.BDTIC.com/ADI
Multiprocessing
HBG
while it is in reset, it
RESET
is deasserted. This allows the host
7
7 – 21