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TROUBLESHOOTING
FLAT LINE SIGNAL DISPLAYED
Figure 18. Bus Check for a 12-Bit ADC
Scenario: After clicking the time domain button, the signal
displayed in the window is a flat line.
1.
Check the power connections.
2.
Verify that the USB cable does not exceed 5 feet in length
or the parallel printer cable is IEEE-1284 compatible.
3.
Check the cable connection between the PC and the FIFO
board. If applicable, ensure the correct parallel port is
selected (LPT1 or LPT2) under Config > Buffer.
4.
If using a parallel port, make sure the Printer Port in the
computer BIOS is set to Standard Bidirectional.
5.
Make sure Channel A, Channel B, or both channels are
selected under Config > FFT.
6.
Check the signal connections and make sure that the clock
is present at the output of the ADC evaluation board.
7.
Verify that data bits are switching at the connection point
between the FIFO and the ADC evaluation board.
8.
Use the Analyze > Bus Check option to ensure all data bits
are switching. See Figure 19 for an example of the AD6645,
14-bit single channel ADC. Note: The left-most bit is the
MSB.
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
9.
Use the ADC data sheet to ensure all jumper connections
are set appropriately on the ADC evaluation board. Ensure
the ADC power-down option is not active.
10. Refer to Table 2, to ensure that all jumpers are set
appropriately.
DISPLAYED SIGNAL UNLIKE ANALOG INPUT
Scenario: After clicking Time Domain, the signal displayed
does not look like the analog input signal.
1.
A fast sinusoidal signal may look like a solid red block in
the time-domain window (due to the number of sine waves
shown). Right click the window to open a hidden menu
where you can zoom in to a closer view of the signal.
2.
Check the cable connection between the PC and the FIFO
board. If applicable, ensure the correct parallel port is
selected (LPT1 or LPT2) under Config > Buffer.
3.
Check the signal connections.
4.
Use the Analyze > Bus Check option to ensure all of the
data bits are switching.
5.
Ensure that the Twos Complement button is set correctly
under Config > FFT. If the Twos Complement box is
checked and the ADC outputs are not in Twos Complement
format, a time-domain plot may look like Figure 20.
6.
Adjust the timing to ensure that the data is captured
correctly. Refer to the Clocking Description section in the
Theory of Operation, and Table 2 for more information.
7.
Try using a very low frequency analog input (for example,
0.1 MHz to 1 MHz) to debug timing issues. For an exact
number of cycles, such as 10, try (10×fs)/M, where fs =
encode frequency and M = sample size (2
8.
Check for problems with the common-mode level at the
analog input by looking at the time data with no analog
input signal.
Rev. 0 | Page 23 of 44
Figure 19. Typical Time Domain Plot
N
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